/*
 *******************************************************************************
 *
 * Copyright (c) 2017 Advanced Micro Devices, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 ******************************************************************************/

#pragma once

typedef enum StereoMode {
SHADER_STEREO_X                          = 0x00000000,
STATE_STEREO_X                           = 0x00000001,
SHADER_STEREO_XYZW                       = 0x00000002,
} StereoMode;

typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL                     = 0x00000000,
ARRAY_LINEAR_ALIGNED                     = 0x00000001,
ARRAY_1D_TILED_THIN1                     = 0x00000002,
ARRAY_1D_TILED_THICK                     = 0x00000003,
ARRAY_2D_TILED_THIN1                     = 0x00000004,
ARRAY_PRT_TILED_THIN1                    = 0x00000005,
ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
ARRAY_2D_TILED_THICK                     = 0x00000007,
ARRAY_2D_TILED_XTHICK                    = 0x00000008,
ARRAY_PRT_TILED_THICK                    = 0x00000009,
ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
ARRAY_3D_TILED_THIN1                     = 0x0000000c,
ARRAY_3D_TILED_THICK                     = 0x0000000d,
ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
} ArrayMode;

typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID                  = 0x00000000,
BUF_DATA_FORMAT_8                        = 0x00000001,
BUF_DATA_FORMAT_16                       = 0x00000002,
BUF_DATA_FORMAT_8_8                      = 0x00000003,
BUF_DATA_FORMAT_32                       = 0x00000004,
BUF_DATA_FORMAT_16_16                    = 0x00000005,
BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
BUF_DATA_FORMAT_32_32                    = 0x0000000b,
BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
} BUF_DATA_FORMAT;

typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM                     = 0x00000000,
BUF_NUM_FORMAT_SNORM                     = 0x00000001,
BUF_NUM_FORMAT_USCALED                   = 0x00000002,
BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
BUF_NUM_FORMAT_UINT                      = 0x00000004,
BUF_NUM_FORMAT_SINT                      = 0x00000005,
BUF_NUM_FORMAT_RESERVED_6__GFX09         = 0x00000006,
BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
} BUF_NUM_FORMAT;

typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
} BankHeight;

typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
} BankInterleaveSize;

typedef enum BankSwapBytes {
CONFIG_128B_SWAPS                        = 0x00000000,
CONFIG_256B_SWAPS                        = 0x00000001,
CONFIG_512B_SWAPS                        = 0x00000002,
CONFIG_1KB_SWAPS                         = 0x00000003,
} BankSwapBytes;

typedef enum BankTiling {
CONFIG_4_BANK                            = 0x00000000,
CONFIG_8_BANK                            = 0x00000001,
} BankTiling;

typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
} BankWidth;

typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1                      = 0x00000000,
ADDR_SURF_BANK_WH_2                      = 0x00000001,
ADDR_SURF_BANK_WH_4                      = 0x00000002,
ADDR_SURF_BANK_WH_8                      = 0x00000003,
} BankWidthHeight;

typedef enum BinEventCntl {
} BinEventCntl;

typedef enum BinSizeExtend {
BIN_SIZE_32_PIXELS                       = 0x00000000,
BIN_SIZE_64_PIXELS                       = 0x00000001,
BIN_SIZE_128_PIXELS                      = 0x00000002,
BIN_SIZE_256_PIXELS                      = 0x00000003,
BIN_SIZE_512_PIXELS                      = 0x00000004,
} BinSizeExtend;

typedef enum BinningMode {
BINNING_ALLOWED                          = 0x00000000,
FORCE_BINNING_ON                         = 0x00000001,
DISABLE_BINNING_USE_LEGACY_SC            = 0x00000003,
} BinningMode;

typedef enum BlendOp {
BLEND_ZERO                               = 0x00000000,
BLEND_ONE                                = 0x00000001,
BLEND_SRC_COLOR                          = 0x00000002,
BLEND_ONE_MINUS_SRC_COLOR                = 0x00000003,
BLEND_SRC_ALPHA                          = 0x00000004,
BLEND_ONE_MINUS_SRC_ALPHA                = 0x00000005,
BLEND_DST_ALPHA                          = 0x00000006,
BLEND_ONE_MINUS_DST_ALPHA                = 0x00000007,
BLEND_DST_COLOR                          = 0x00000008,
BLEND_ONE_MINUS_DST_COLOR                = 0x00000009,
BLEND_SRC_ALPHA_SATURATE                 = 0x0000000a,
BLEND_BOTH_SRC_ALPHA                     = 0x0000000b,
BLEND_BOTH_INV_SRC_ALPHA                 = 0x0000000c,
BLEND_CONSTANT_COLOR                     = 0x0000000d,
BLEND_ONE_MINUS_CONSTANT_COLOR           = 0x0000000e,
BLEND_SRC1_COLOR                         = 0x0000000f,
BLEND_INV_SRC1_COLOR                     = 0x00000010,
BLEND_SRC1_ALPHA                         = 0x00000011,
BLEND_INV_SRC1_ALPHA                     = 0x00000012,
BLEND_CONSTANT_ALPHA                     = 0x00000013,
BLEND_ONE_MINUS_CONSTANT_ALPHA           = 0x00000014,
} BlendOp;

typedef enum BlendOpt {
FORCE_OPT_AUTO                           = 0x00000000,
FORCE_OPT_DISABLE                        = 0x00000001,
FORCE_OPT_ENABLE_IF_SRC_A_0              = 0x00000002,
FORCE_OPT_ENABLE_IF_SRC_RGB_0            = 0x00000003,
FORCE_OPT_ENABLE_IF_SRC_ARGB_0           = 0x00000004,
FORCE_OPT_ENABLE_IF_SRC_A_1              = 0x00000005,
FORCE_OPT_ENABLE_IF_SRC_RGB_1            = 0x00000006,
FORCE_OPT_ENABLE_IF_SRC_ARGB_1           = 0x00000007,
} BlendOpt;

typedef enum CBMode {
CB_DISABLE                               = 0x00000000,
CB_NORMAL                                = 0x00000001,
CB_ELIMINATE_FAST_CLEAR                  = 0x00000002,
CB_RESOLVE                               = 0x00000003,
CB_DECOMPRESS                            = 0x00000004,
CB_FMASK_DECOMPRESS                      = 0x00000005,
CB_DCC_DECOMPRESS                        = 0x00000006,
} CBMode;

typedef enum CBPerfClearFilterSel {
CB_PERF_CLEAR_FILTER_SEL_NONCLEAR        = 0x00000000,
CB_PERF_CLEAR_FILTER_SEL_CLEAR           = 0x00000001,
} CBPerfClearFilterSel;

typedef enum CBPerfOpFilterSel {
CB_PERF_OP_FILTER_SEL_WRITE_ONLY         = 0x00000000,
CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION  = 0x00000001,
CB_PERF_OP_FILTER_SEL_RESOLVE            = 0x00000002,
CB_PERF_OP_FILTER_SEL_DECOMPRESS         = 0x00000003,
CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS   = 0x00000004,
CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
} CBPerfOpFilterSel;

typedef enum CBPerfSel {
CB_PERF_SEL_NONE                         = 0x00000000,
CB_PERF_SEL_BUSY                         = 0x00000001,
CB_PERF_SEL_CORE_SCLK_VLD                = 0x00000002,
CB_PERF_SEL_REG_SCLK0_VLD                = 0x00000003,
CB_PERF_SEL_REG_SCLK1_VLD                = 0x00000004,
CB_PERF_SEL_DRAWN_QUAD                   = 0x00000005,
CB_PERF_SEL_DRAWN_PIXEL                  = 0x00000006,
CB_PERF_SEL_DRAWN_QUAD_FRAGMENT          = 0x00000007,
CB_PERF_SEL_DRAWN_TILE                   = 0x00000008,
CB_PERF_SEL_DB_CB_TILE_VALID_READY       = 0x00000009,
CB_PERF_SEL_DB_CB_TILE_VALID_READYB      = 0x0000000a,
CB_PERF_SEL_DB_CB_TILE_VALIDB_READY      = 0x0000000b,
CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB     = 0x0000000c,
CB_PERF_SEL_CM_FC_TILE_VALID_READY       = 0x0000000d,
CB_PERF_SEL_CM_FC_TILE_VALID_READYB      = 0x0000000e,
CB_PERF_SEL_CM_FC_TILE_VALIDB_READY      = 0x0000000f,
CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB     = 0x00000010,
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY  = 0x00000011,
CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
CB_PERF_SEL_DB_CB_LQUAD_VALID_READY      = 0x00000013,
CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB     = 0x00000014,
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY     = 0x00000015,
CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB    = 0x00000016,
CB_PERF_SEL_LQUAD_NO_TILE                = 0x00000017,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R  = 0x00000018,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e,
CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021,
CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY    = 0x00000024,
CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB   = 0x00000025,
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY   = 0x00000026,
CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB  = 0x00000027,
CB_PERF_SEL_FOP_IN_VALID_READY           = 0x00000028,
CB_PERF_SEL_FOP_IN_VALID_READYB          = 0x00000029,
CB_PERF_SEL_FOP_IN_VALIDB_READY          = 0x0000002a,
CB_PERF_SEL_FOP_IN_VALIDB_READYB         = 0x0000002b,
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY   = 0x0000002c,
CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB  = 0x0000002d,
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY  = 0x0000002e,
CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY    = 0x00000030,
CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB   = 0x00000031,
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY   = 0x00000032,
CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB  = 0x00000033,
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY    = 0x00000034,
CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB   = 0x00000035,
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY   = 0x00000036,
CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB  = 0x00000037,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
CB_PERF_SEL_CC_BC_CS_FRAG_VALID          = 0x00000040,
CB_PERF_SEL_CM_CACHE_HIT                 = 0x00000041,
CB_PERF_SEL_CM_CACHE_TAG_MISS            = 0x00000042,
CB_PERF_SEL_CM_CACHE_SECTOR_MISS         = 0x00000043,
CB_PERF_SEL_CM_CACHE_REEVICTION_STALL    = 0x00000044,
CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045,
CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047,
CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL   = 0x00000048,
CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL  = 0x00000049,
CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL    = 0x0000004a,
CB_PERF_SEL_CM_CACHE_STALL               = 0x0000004b,
CB_PERF_SEL_CM_CACHE_FLUSH               = 0x0000004c,
CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED        = 0x0000004d,
CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED     = 0x0000004e,
CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
CB_PERF_SEL_FC_CACHE_HIT                 = 0x00000050,
CB_PERF_SEL_FC_CACHE_TAG_MISS            = 0x00000051,
CB_PERF_SEL_FC_CACHE_SECTOR_MISS         = 0x00000052,
CB_PERF_SEL_FC_CACHE_REEVICTION_STALL    = 0x00000053,
CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054,
CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056,
CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL   = 0x00000057,
CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL  = 0x00000058,
CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL    = 0x00000059,
CB_PERF_SEL_FC_CACHE_STALL               = 0x0000005a,
CB_PERF_SEL_FC_CACHE_FLUSH               = 0x0000005b,
CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED        = 0x0000005c,
CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED     = 0x0000005d,
CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
CB_PERF_SEL_CC_CACHE_HIT                 = 0x0000005f,
CB_PERF_SEL_CC_CACHE_TAG_MISS            = 0x00000060,
CB_PERF_SEL_CC_CACHE_SECTOR_MISS         = 0x00000061,
CB_PERF_SEL_CC_CACHE_REEVICTION_STALL    = 0x00000062,
CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063,
CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065,
CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL   = 0x00000066,
CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL  = 0x00000067,
CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL    = 0x00000068,
CB_PERF_SEL_CC_CACHE_STALL               = 0x00000069,
CB_PERF_SEL_CC_CACHE_FLUSH               = 0x0000006a,
CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED        = 0x0000006b,
CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED     = 0x0000006c,
CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC__GFX09 = 0x0000006f,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY__GFX09 = 0x00000070,
CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB__GFX09 = 0x00000071,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY__GFX09 = 0x00000072,
CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB__GFX09 = 0x00000073,
CB_PERF_SEL_CM_MC_WRITE_REQUEST__GFX09   = 0x00000074,
CB_PERF_SEL_FC_MC_WRITE_REQUEST__GFX09   = 0x00000075,
CB_PERF_SEL_CC_MC_WRITE_REQUEST__GFX09   = 0x00000076,
CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT__GFX09 = 0x00000077,
CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT__GFX09 = 0x00000078,
CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT__GFX09 = 0x00000079,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY__GFX09 = 0x0000007a,
CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB__GFX09 = 0x0000007b,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY__GFX09 = 0x0000007c,
CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB__GFX09 = 0x0000007d,
CB_PERF_SEL_CM_MC_READ_REQUEST__GFX09    = 0x0000007e,
CB_PERF_SEL_FC_MC_READ_REQUEST__GFX09    = 0x0000007f,
CB_PERF_SEL_CC_MC_READ_REQUEST__GFX09    = 0x00000080,
CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT__GFX09 = 0x00000081,
CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT__GFX09 = 0x00000082,
CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT__GFX09 = 0x00000083,
CB_PERF_SEL_CM_TQ_FULL__GFX09            = 0x00000084,
CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL__GFX09 = 0x00000085,
CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL      = 0x00000086,
CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL      = 0x00000087,
CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088,
CB_PERF_SEL_FOP_FMASK_RAW_STALL__GFX09   = 0x00000089,
CB_PERF_SEL_FOP_FMASK_BYPASS_STALL__GFX09 = 0x0000008a,
CB_PERF_SEL_CC_SF_FULL__GFX09            = 0x0000008b,
CB_PERF_SEL_CC_RB_FULL__GFX09            = 0x0000008c,
CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL__GFX09 = 0x0000008d,
CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL__GFX09 = 0x0000008e,
CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL__GFX09 = 0x0000008f,
CB_PERF_SEL_EVENT__GFX09                 = 0x00000090,
CB_PERF_SEL_EVENT_CACHE_FLUSH_TS__GFX09  = 0x00000091,
CB_PERF_SEL_EVENT_CONTEXT_DONE__GFX09    = 0x00000092,
CB_PERF_SEL_EVENT_CACHE_FLUSH__GFX09     = 0x00000093,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__GFX09 = 0x00000094,
CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT__GFX09 = 0x00000095,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS__GFX09 = 0x00000096,
CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META__GFX09 = 0x00000097,
CB_PERF_SEL_CC_SURFACE_SYNC__GFX09       = 0x00000098,
CB_PERF_SEL_CMASK_READ_DATA_0xC__GFX09   = 0x00000099,
CB_PERF_SEL_CMASK_READ_DATA_0xD__GFX09   = 0x0000009a,
CB_PERF_SEL_CMASK_READ_DATA_0xE__GFX09   = 0x0000009b,
CB_PERF_SEL_CMASK_READ_DATA_0xF__GFX09   = 0x0000009c,
CB_PERF_SEL_CMASK_WRITE_DATA_0xC__GFX09  = 0x0000009d,
CB_PERF_SEL_CMASK_WRITE_DATA_0xD__GFX09  = 0x0000009e,
CB_PERF_SEL_CMASK_WRITE_DATA_0xE__GFX09  = 0x0000009f,
CB_PERF_SEL_CMASK_WRITE_DATA_0xF__GFX09  = 0x000000a0,
CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT__GFX09 = 0x000000a1,
CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT__GFX09 = 0x000000a2,
CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT__GFX09 = 0x000000a3,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__GFX09 = 0x000000a4,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000a5,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000a6,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000a7,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000a8,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000a9,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000aa,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__GFX09 = 0x000000ab,
CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__GFX09 = 0x000000ac,
CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000ad,
CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000ae,
CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000af,
CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000b0,
CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000b1,
CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000b2,
CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__GFX09 = 0x000000b3,
CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT__GFX09 = 0x000000b4,
CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS__GFX09 = 0x000000b5,
CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS__GFX09 = 0x000000b6,
CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS__GFX09 = 0x000000b7,
CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS__GFX09 = 0x000000b8,
CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS__GFX09 = 0x000000b9,
CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS__GFX09 = 0x000000ba,
CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT__GFX09 = 0x000000bb,
CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS__GFX09 = 0x000000bc,
CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS__GFX09 = 0x000000bd,
CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS__GFX09 = 0x000000be,
CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS__GFX09 = 0x000000bf,
CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS__GFX09 = 0x000000c0,
CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS__GFX09 = 0x000000c1,
CB_PERF_SEL_QUAD_READS_FRAGMENT_0__GFX09 = 0x000000c2,
CB_PERF_SEL_QUAD_READS_FRAGMENT_1__GFX09 = 0x000000c3,
CB_PERF_SEL_QUAD_READS_FRAGMENT_2__GFX09 = 0x000000c4,
CB_PERF_SEL_QUAD_READS_FRAGMENT_3__GFX09 = 0x000000c5,
CB_PERF_SEL_QUAD_READS_FRAGMENT_4__GFX09 = 0x000000c6,
CB_PERF_SEL_QUAD_READS_FRAGMENT_5__GFX09 = 0x000000c7,
CB_PERF_SEL_QUAD_READS_FRAGMENT_6__GFX09 = 0x000000c8,
CB_PERF_SEL_QUAD_READS_FRAGMENT_7__GFX09 = 0x000000c9,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0__GFX09 = 0x000000ca,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1__GFX09 = 0x000000cb,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2__GFX09 = 0x000000cc,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3__GFX09 = 0x000000cd,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4__GFX09 = 0x000000ce,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5__GFX09 = 0x000000cf,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6__GFX09 = 0x000000d0,
CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7__GFX09 = 0x000000d1,
CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST__GFX09 = 0x000000d2,
CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS__GFX09 = 0x000000d3,
CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS__GFX09 = 0x000000d4,
CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED__GFX09 = 0x000000d5,
CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED__GFX09 = 0x000000d6,
CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED__GFX09 = 0x000000d7,
CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST__GFX09 = 0x000000d8,
CB_PERF_SEL_DRAWN_BUSY__GFX09            = 0x000000d9,
CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY__GFX09 = 0x000000da,
CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY__GFX09 = 0x000000db,
CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY__GFX09 = 0x000000dc,
CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY__GFX09 = 0x000000dd,
CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED__GFX09 = 0x000000de,
CB_PERF_SEL_FC_SEQUENCER_CLEAR__GFX09    = 0x000000df,
CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR__GFX09 = 0x000000e0,
CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS__GFX09 = 0x000000e1,
CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__GFX09 = 0x000000e2,
CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL__GFX09 = 0x000000e3,
CB_PERF_SEL_FC_DOC_IS_STALLED__GFX09     = 0x000000e4,
CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED__GFX09 = 0x000000e5,
CB_PERF_SEL_FC_DOC_MRTS_COMBINED__GFX09  = 0x000000e6,
CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS__GFX09 = 0x000000e7,
CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT__GFX09  = 0x000000e8,
CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS__GFX09 = 0x000000e9,
CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT__GFX09  = 0x000000ea,
CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL__GFX09 = 0x000000eb,
CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR__GFX09 = 0x000000ec,
CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS__GFX09 = 0x000000ed,
CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS__GFX09 = 0x000000ee,
CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS__GFX09 = 0x000000ef,
CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS__GFX09 = 0x000000f0,
CB_PERF_SEL_FC_DCC_CACHE_HIT__GFX09      = 0x000000f1,
CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS__GFX09 = 0x000000f2,
CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS__GFX09 = 0x000000f3,
CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL__GFX09 = 0x000000f4,
CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__GFX09 = 0x000000f5,
CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__GFX09 = 0x000000f6,
CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__GFX09 = 0x000000f7,
CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL__GFX09 = 0x000000f8,
CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL__GFX09 = 0x000000f9,
CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL__GFX09 = 0x000000fa,
CB_PERF_SEL_FC_DCC_CACHE_STALL__GFX09    = 0x000000fb,
CB_PERF_SEL_FC_DCC_CACHE_FLUSH__GFX09    = 0x000000fc,
CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED__GFX09 = 0x000000fd,
CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED__GFX09 = 0x000000fe,
CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED__GFX09 = 0x000000ff,
CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT__GFX09 = 0x00000100,
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST__GFX09 = 0x00000101,
CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__GFX09 = 0x00000102,
CB_PERF_SEL_FC_MC_DCC_READ_REQUEST__GFX09 = 0x00000103,
CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__GFX09 = 0x00000104,
CB_PERF_SEL_CC_DCC_RDREQ_STALL__GFX09    = 0x00000105,
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN__GFX09 = 0x00000106,
CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT__GFX09 = 0x00000107,
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN__GFX09 = 0x00000108,
CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT__GFX09 = 0x00000109,
CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR__GFX09 = 0x0000010a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1__GFX09 = 0x0000010b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2__GFX09 = 0x0000010c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x0000010d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1__GFX09 = 0x0000010e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1__GFX09 = 0x0000010f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2__GFX09 = 0x00000110,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1__GFX09 = 0x00000111,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x00000112,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x00000113,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1__GFX09 = 0x00000114,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2__GFX09 = 0x00000115,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2__GFX09 = 0x00000116,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2__GFX09 = 0x00000117,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x00000118,
CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1__GFX09 = 0x00000119,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1__GFX09 = 0x0000011a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2__GFX09 = 0x0000011b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3__GFX09 = 0x0000011c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4__GFX09 = 0x0000011d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1__GFX09 = 0x0000011e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2__GFX09 = 0x0000011f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3__GFX09 = 0x00000120,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4__GFX09 = 0x00000121,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1__GFX09 = 0x00000122,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2__GFX09 = 0x00000123,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3__GFX09 = 0x00000124,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4__GFX09 = 0x00000125,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1__GFX09 = 0x00000126,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2__GFX09 = 0x00000127,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3__GFX09 = 0x00000128,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1__GFX09 = 0x00000129,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2__GFX09 = 0x0000012a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3__GFX09 = 0x0000012b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4__GFX09 = 0x0000012c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1__GFX09 = 0x0000012d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2__GFX09 = 0x0000012e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3__GFX09 = 0x0000012f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4__GFX09 = 0x00000130,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1__GFX09 = 0x00000131,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2__GFX09 = 0x00000132,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3__GFX09 = 0x00000133,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4__GFX09 = 0x00000134,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1__GFX09 = 0x00000135,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2__GFX09 = 0x00000136,
CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3__GFX09 = 0x00000137,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1__GFX09 = 0x00000138,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1__GFX09 = 0x00000139,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1__GFX09 = 0x0000013a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1__GFX09 = 0x0000013b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1__GFX09 = 0x0000013c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1__GFX09 = 0x0000013d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1__GFX09 = 0x0000013e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1__GFX09 = 0x0000013f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2__GFX09 = 0x00000140,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2__GFX09 = 0x00000141,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2__GFX09 = 0x00000142,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2__GFX09 = 0x00000143,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2__GFX09 = 0x00000144,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2__GFX09 = 0x00000145,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2__GFX09 = 0x00000146,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1__GFX09 = 0x00000147,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1__GFX09 = 0x00000148,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1__GFX09 = 0x00000149,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1__GFX09 = 0x0000014a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2__GFX09 = 0x0000014b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2__GFX09 = 0x0000014c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2__GFX09 = 0x0000014d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x0000014e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x0000014f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x00000150,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2__GFX09 = 0x00000151,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x00000152,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x00000153,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x00000154,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1__GFX09 = 0x00000155,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1__GFX09 = 0x00000156,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2__GFX09 = 0x00000157,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3__GFX09 = 0x00000158,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4__GFX09 = 0x00000159,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5__GFX09 = 0x0000015a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6__GFX09 = 0x0000015b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0__GFX09 = 0x0000015c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1__GFX09 = 0x0000015d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1__GFX09 = 0x0000015e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2__GFX09 = 0x0000015f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3__GFX09 = 0x00000160,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4__GFX09 = 0x00000161,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5__GFX09 = 0x00000162,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0__GFX09 = 0x00000163,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1__GFX09 = 0x00000164,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1__GFX09 = 0x00000165,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1__GFX09 = 0x00000166,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1__GFX09 = 0x00000167,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1__GFX09 = 0x00000168,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1__GFX09 = 0x00000169,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1__GFX09 = 0x0000016a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1__GFX09 = 0x0000016b,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1__GFX09 = 0x0000016c,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2__GFX09 = 0x0000016d,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2__GFX09 = 0x0000016e,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2__GFX09 = 0x0000016f,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2__GFX09 = 0x00000170,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2__GFX09 = 0x00000171,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2__GFX09 = 0x00000172,
CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2__GFX09 = 0x00000173,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1__GFX09 = 0x00000174,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2__GFX09 = 0x00000175,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3__GFX09 = 0x00000176,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4__GFX09 = 0x00000177,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5__GFX09 = 0x00000178,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6__GFX09 = 0x00000179,
CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7__GFX09 = 0x0000017a,
CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED__GFX09 = 0x0000017b,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1__GFX09 = 0x0000017c,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1__GFX09 = 0x0000017d,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2__GFX09 = 0x0000017e,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3__GFX09 = 0x0000017f,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1__GFX09 = 0x00000180,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2__GFX09 = 0x00000181,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3__GFX09 = 0x00000182,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4__GFX09 = 0x00000183,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5__GFX09 = 0x00000184,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1__GFX09 = 0x00000185,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2__GFX09 = 0x00000186,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3__GFX09 = 0x00000187,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4__GFX09 = 0x00000188,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5__GFX09 = 0x00000189,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6__GFX09 = 0x0000018a,
CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7__GFX09 = 0x0000018b,
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH__GFX09 = 0x0000018c,
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT__GFX09 = 0x0000018d,
CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT__GFX09 = 0x0000018e,
CB_PERF_SEL_RBP_SPLIT_MICROTILE__GFX09   = 0x0000018f,
CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK__GFX09 = 0x00000190,
CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK__GFX09 = 0x00000191,
CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING__GFX09 = 0x00000192,
CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS__GFX09 = 0x00000193,
CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD__GFX09 = 0x00000194,
CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD__GFX09 = 0x000001b5,
} CBPerfSel;

typedef enum CLKGATE_BASE_MODE {
MULT_8                                   = 0x00000000,
MULT_16                                  = 0x00000001,
} CLKGATE_BASE_MODE;

typedef enum CLKGATE_SM_MODE {
ON_SEQ                                   = 0x00000000,
OFF_SEQ                                  = 0x00000001,
PROG_SEQ                                 = 0x00000002,
READ_SEQ                                 = 0x00000003,
SM_MODE_RESERVED                         = 0x00000004,
} CLKGATE_SM_MODE;

typedef enum CPC_PERFCOUNT_SEL {
CPC_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE     = 0x00000001,
CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION   = 0x00000002,
CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE     = 0x00000003,
CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE     = 0x00000004,
CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE     = 0x00000005,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ__GFX09 = 0x00000009,
CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE__GFX09 = 0x0000000a,
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ  = 0x0000000b,
CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE  = 0x0000000d,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ__GFX09 = 0x00000011,
CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE__GFX09 = 0x00000012,
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ  = 0x00000013,
CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE  = 0x00000015,
CPC_PERF_SEL_ME2_DC1_SPI_BUSY            = 0x00000022,
} CPC_PERFCOUNT_SEL;

typedef enum CPF_PERFCOUNT_SEL {
CPF_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING  = 0x00000004,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1   = 0x00000005,
CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2   = 0x00000006,
CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR         = 0x00000009,
CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR      = 0x0000000a,
CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x0000000b,
CPF_PERF_SEL_GRBM_DWORDS_SENT            = 0x0000000c,
CPF_PERF_SEL_DYNAMIC_CLOCK_VALID         = 0x0000000d,
CPF_PERF_SEL_REGISTER_CLOCK_VALID        = 0x0000000e,
CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND__GFX09 = 0x0000000f,
CPF_PERF_SEL_MIU_READ_REQUEST_SEND__GFX09 = 0x00000010,
CPF_PERF_SEL_CPF_UTCL2IU_STALL__GFX09    = 0x0000001f,
} CPF_PERFCOUNT_SEL;

typedef enum CPG_PERFCOUNT_SEL {
CPG_PERF_SEL_ALWAYS_COUNT                = 0x00000000,
CPG_PERF_SEL_RBIU_FIFO_FULL              = 0x00000001,
CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR     = 0x00000002,
CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL  = 0x00000003,
CPG_PERF_SEL_CP_GRBM_DWORDS_SENT         = 0x00000004,
CPG_PERF_SEL_ME_PARSER_BUSY              = 0x00000005,
CPG_PERF_SEL_COUNT_TYPE0_PACKETS         = 0x00000006,
CPG_PERF_SEL_COUNT_TYPE3_PACKETS         = 0x00000007,
CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS    = 0x00000008,
CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS      = 0x00000009,
CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS  = 0x0000000a,
CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS  = 0x0000000b,
CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ     = 0x0000000c,
CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ    = 0x0000000d,
CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX  = 0x0000000e,
CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS__GFX09 = 0x00000010,
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE__GFX09 = 0x00000011,
CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM__GFX09 = 0x00000012,
CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY__GFX09 = 0x00000013,
CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY__GFX09 = 0x00000014,
CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY__GFX09 = 0x00000015,
CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ__GFX09 = 0x00000016,
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP__GFX09 = 0x00000017,
CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ__GFX09 = 0x00000018,
CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX__GFX09 = 0x00000019,
CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU__GFX09 = 0x0000001a,
CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS__GFX09 = 0x0000001b,
CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH__GFX09 = 0x0000001c,
CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER__GFX09 = 0x0000001d,
CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER__GFX09 = 0x0000001e,
CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS__GFX09 = 0x0000001f,
CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY__GFX09 = 0x00000020,
CPG_PERF_SEL_DYNAMIC_CLK_VALID__GFX09    = 0x00000021,
CPG_PERF_SEL_REGISTER_CLK_VALID__GFX09   = 0x00000022,
CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT__GFX09 = 0x00000023,
CPG_PERF_SEL_MIU_READ_REQUEST_SENT__GFX09 = 0x00000024,
CPG_PERF_SEL_CE_STALL_RAM_DUMP__GFX09    = 0x00000025,
CPG_PERF_SEL_CE_STALL_RAM_WRITE__GFX09   = 0x00000026,
CPG_PERF_SEL_CE_STALL_ON_INC_FIFO__GFX09 = 0x00000027,
CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO__GFX09 = 0x00000028,
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU__GFX09 = 0x00000029,
CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ__GFX09 = 0x0000002a,
CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG__GFX09 = 0x0000002b,
CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER__GFX09 = 0x0000002c,
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE__GFX09 = 0x0000002d,
CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS__GFX09 = 0x0000002e,
CPG_PERF_SEL_CPG_UTCL2IU_STALL           = 0x0000003b,
} CPG_PERFCOUNT_SEL;

typedef enum CP_ALPHA_TAG_RAM_SEL {
CPG_TAG_RAM                              = 0x00000000,
CPC_TAG_RAM                              = 0x00000001,
CPF_TAG_RAM                              = 0x00000002,
RSV_TAG_RAM                              = 0x00000003,
} CP_ALPHA_TAG_RAM_SEL;

typedef enum CP_ME_ID {
ME_ID0                                   = 0x00000000,
ME_ID1                                   = 0x00000001,
ME_ID2                                   = 0x00000002,
ME_ID3                                   = 0x00000003,
} CP_ME_ID;

typedef enum CP_PERFMON_ENABLE_MODE {
CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT      = 0x00000000,
CP_PERFMON_ENABLE_MODE_RESERVED_1        = 0x00000001,
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
} CP_PERFMON_ENABLE_MODE;

typedef enum CP_PERFMON_STATE {
CP_PERFMON_STATE_DISABLE_AND_RESET       = 0x00000000,
CP_PERFMON_STATE_START_COUNTING          = 0x00000001,
CP_PERFMON_STATE_STOP_COUNTING           = 0x00000002,
CP_PERFMON_STATE_RESERVED_3              = 0x00000003,
CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM  = 0x00000005,
} CP_PERFMON_STATE;

typedef enum CP_PIPE_ID {
PIPE_ID0                                 = 0x00000000,
PIPE_ID1                                 = 0x00000001,
PIPE_ID2                                 = 0x00000002,
PIPE_ID3                                 = 0x00000003,
} CP_PIPE_ID;

typedef enum CP_RING_ID {
RINGID0                                  = 0x00000000,
RINGID1                                  = 0x00000001,
RINGID2                                  = 0x00000002,
RINGID3                                  = 0x00000003,
} CP_RING_ID;

typedef enum CSDATA_TYPE {
CSDATA_TYPE_TG                           = 0x00000000,
CSDATA_TYPE_STATE                        = 0x00000001,
CSDATA_TYPE_EVENT                        = 0x00000002,
CSDATA_TYPE_PRIVATE                      = 0x00000003,
} CSDATA_TYPE;

typedef enum CmaskAddr {
CMASK_ADDR_TILED                         = 0x00000000,
CMASK_ADDR_LINEAR                        = 0x00000001,
CMASK_ADDR_COMPATIBLE                    = 0x00000002,
} CmaskAddr;

typedef enum CmaskCode {
CMASK_CLR00_F0                           = 0x00000000,
CMASK_CLR00_F1                           = 0x00000001,
CMASK_CLR00_F2                           = 0x00000002,
CMASK_CLR00_FX                           = 0x00000003,
CMASK_CLR01_F0                           = 0x00000004,
CMASK_CLR01_F1                           = 0x00000005,
CMASK_CLR01_F2                           = 0x00000006,
CMASK_CLR01_FX                           = 0x00000007,
CMASK_CLR10_F0                           = 0x00000008,
CMASK_CLR10_F1                           = 0x00000009,
CMASK_CLR10_F2                           = 0x0000000a,
CMASK_CLR10_FX                           = 0x0000000b,
CMASK_CLR11_F0                           = 0x0000000c,
CMASK_CLR11_F1                           = 0x0000000d,
CMASK_CLR11_F2                           = 0x0000000e,
CMASK_CLR11_FX                           = 0x0000000f,
} CmaskCode;

typedef enum CmaskMode {
CMASK_CLEAR_NONE                         = 0x00000000,
CMASK_CLEAR_ONE                          = 0x00000001,
CMASK_CLEAR_ALL                          = 0x00000002,
CMASK_ANY_EXPANDED                       = 0x00000003,
CMASK_ALPHA0_FRAG1                       = 0x00000004,
CMASK_ALPHA0_FRAG2                       = 0x00000005,
CMASK_ALPHA0_FRAG4                       = 0x00000006,
CMASK_ALPHA0_FRAGS                       = 0x00000007,
CMASK_ALPHA1_FRAG1                       = 0x00000008,
CMASK_ALPHA1_FRAG2                       = 0x00000009,
CMASK_ALPHA1_FRAG4                       = 0x0000000a,
CMASK_ALPHA1_FRAGS                       = 0x0000000b,
CMASK_ALPHAX_FRAG1                       = 0x0000000c,
CMASK_ALPHAX_FRAG2                       = 0x0000000d,
CMASK_ALPHAX_FRAG4                       = 0x0000000e,
CMASK_ALPHAX_FRAGS                       = 0x0000000f,
} CmaskMode;

typedef enum ColorArray {
ARRAY_2D_ALT_COLOR                       = 0x00000000,
ARRAY_2D_COLOR                           = 0x00000001,
ARRAY_3D_SLICE_COLOR                     = 0x00000003,
} ColorArray;

typedef enum ColorFormat {
COLOR_INVALID                            = 0x00000000,
COLOR_8                                  = 0x00000001,
COLOR_16                                 = 0x00000002,
COLOR_8_8                                = 0x00000003,
COLOR_32                                 = 0x00000004,
COLOR_16_16                              = 0x00000005,
COLOR_10_11_11                           = 0x00000006,
COLOR_11_11_10                           = 0x00000007,
COLOR_10_10_10_2                         = 0x00000008,
COLOR_2_10_10_10                         = 0x00000009,
COLOR_8_8_8_8                            = 0x0000000a,
COLOR_32_32                              = 0x0000000b,
COLOR_16_16_16_16                        = 0x0000000c,
COLOR_RESERVED_13                        = 0x0000000d,
COLOR_32_32_32_32                        = 0x0000000e,
COLOR_RESERVED_15                        = 0x0000000f,
COLOR_5_6_5                              = 0x00000010,
COLOR_1_5_5_5                            = 0x00000011,
COLOR_5_5_5_1                            = 0x00000012,
COLOR_4_4_4_4                            = 0x00000013,
COLOR_8_24                               = 0x00000014,
COLOR_24_8                               = 0x00000015,
COLOR_X24_8_32_FLOAT                     = 0x00000016,
COLOR_RESERVED_23                        = 0x00000017,
COLOR_RESERVED_24                        = 0x00000018,
COLOR_RESERVED_25                        = 0x00000019,
COLOR_RESERVED_26                        = 0x0000001a,
COLOR_RESERVED_27                        = 0x0000001b,
COLOR_RESERVED_28                        = 0x0000001c,
COLOR_RESERVED_29                        = 0x0000001d,
COLOR_RESERVED_30                        = 0x0000001e,
} ColorFormat;

typedef enum ColorTransform {
DCC_CT_AUTO                              = 0x00000000,
DCC_CT_NONE                              = 0x00000001,
ABGR_TO_A_BG_G_RB                        = 0x00000002,
BGRA_TO_BG_G_RB_A                        = 0x00000003,
} ColorTransform;

typedef enum CombFunc {
COMB_DST_PLUS_SRC                        = 0x00000000,
COMB_SRC_MINUS_DST                       = 0x00000001,
COMB_MIN_DST_SRC                         = 0x00000002,
COMB_MAX_DST_SRC                         = 0x00000003,
COMB_DST_MINUS_SRC                       = 0x00000004,
} CombFunc;

typedef enum CompareFrag {
FRAG_NEVER                               = 0x00000000,
FRAG_LESS                                = 0x00000001,
FRAG_EQUAL                               = 0x00000002,
FRAG_LEQUAL                              = 0x00000003,
FRAG_GREATER                             = 0x00000004,
FRAG_NOTEQUAL                            = 0x00000005,
FRAG_GEQUAL                              = 0x00000006,
FRAG_ALWAYS                              = 0x00000007,
} CompareFrag;

typedef enum CompareRef {
REF_NEVER                                = 0x00000000,
REF_LESS                                 = 0x00000001,
REF_EQUAL                                = 0x00000002,
REF_LEQUAL                               = 0x00000003,
REF_GREATER                              = 0x00000004,
REF_NOTEQUAL                             = 0x00000005,
REF_GEQUAL                               = 0x00000006,
REF_ALWAYS                               = 0x00000007,
} CompareRef;

typedef enum ConservativeZExport {
EXPORT_ANY_Z                             = 0x00000000,
EXPORT_LESS_THAN_Z                       = 0x00000001,
EXPORT_GREATER_THAN_Z                    = 0x00000002,
EXPORT_RESERVED                          = 0x00000003,
} ConservativeZExport;

typedef enum CovToShaderSel {
INPUT_COVERAGE                           = 0x00000000,
INPUT_INNER_COVERAGE                     = 0x00000001,
RAW                                      = 0x00000003,
} CovToShaderSel;

typedef enum DFSMFlushEvents {
DB_CACHE_FLUSH                           = 0x00000002,
} DFSMFlushEvents;

typedef enum DSM_ENABLE_ERROR_INJECT {
} DSM_ENABLE_ERROR_INJECT;

typedef enum DSM_SELECT_INJECT_DELAY {
} DSM_SELECT_INJECT_DELAY;

typedef enum DSM_SINGLE_WRITE {
DSM_SINGLE_WRITE_EN                      = 0x00000001,
} DSM_SINGLE_WRITE;

typedef enum DbMemArbWatermarks {
} DbMemArbWatermarks;

typedef enum DbPRTFaultBehavior {
FAULT_ZERO                               = 0x00000000,
} DbPRTFaultBehavior;

typedef enum DbPSLControl {
PSLC_AUTO                                = 0x00000000,
PSLC_ON_HANG_ONLY                        = 0x00000001,
PSLC_ASAP                                = 0x00000002,
PSLC_COUNTDOWN                           = 0x00000003,
} DbPSLControl;

typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH                       = 0x00000000,
ARRAY_2D_DEPTH                           = 0x00000001,
} DepthArray;

typedef enum DepthFormat {
DEPTH_INVALID                            = 0x00000000,
DEPTH_16                                 = 0x00000001,
DEPTH_X8_24                              = 0x00000002,
DEPTH_8_24                               = 0x00000003,
DEPTH_X8_24_FLOAT                        = 0x00000004,
DEPTH_8_24_FLOAT                         = 0x00000005,
DEPTH_32_FLOAT                           = 0x00000006,
DEPTH_X24_8_32_FLOAT                     = 0x00000007,
} DepthFormat;

typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU                          = 0x00000004,
} ENUM_NUM_SIMD_PER_CU;

typedef enum ForceControl {
FORCE_OFF                                = 0x00000000,
FORCE_ENABLE                             = 0x00000001,
FORCE_DISABLE                            = 0x00000002,
FORCE_RESERVED                           = 0x00000003,
} ForceControl;

typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL                       = 0x00000000,
GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
GATCL1_TYPE_BYPASS                       = 0x00000002,
} GATCL1RequestType;

typedef enum GB_EDC_DED_MODE {
GB_EDC_DED_MODE_LOG                      = 0x00000000,
GB_EDC_DED_MODE_HALT                     = 0x00000001,
GB_EDC_DED_MODE_INT_HALT                 = 0x00000002,
} GB_EDC_DED_MODE;

typedef enum GDS_PERFCOUNT_SELECT {
GDS_PERF_SEL_DS_ADDR_CONFL               = 0,
GDS_PERF_SEL_DS_BANK_CONFL               = 1,
GDS_PERF_SEL_WBUF_FLUSH                  = 2,
GDS_PERF_SEL_WR_COMP                     = 3,
GDS_PERF_SEL_WBUF_WR                     = 4,
GDS_PERF_SEL_RBUF_HIT                    = 5,
GDS_PERF_SEL_RBUF_MISS                   = 6,
GDS_PERF_SEL_SE0_SH0_NORET               = 7,
GDS_PERF_SEL_SE0_SH0_RET                 = 8,
GDS_PERF_SEL_SE0_SH0_ORD_CNT             = 9,
GDS_PERF_SEL_SE0_SH0_2COMP_REQ           = 10,
GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID      = 11,
GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID      = 12,
GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD    = 13,
GDS_PERF_SEL_SE0_SH0_GDS_WR_OP           = 14,
GDS_PERF_SEL_SE0_SH0_GDS_RD_OP           = 15,
GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP         = 16,
GDS_PERF_SEL_SE0_SH0_GDS_REL_OP          = 17,
GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP       = 18,
GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP         = 19,
GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP        = 20,
GDS_PERF_SEL_SE0_SH1_NORET               = 21,
GDS_PERF_SEL_SE0_SH1_RET                 = 22,
GDS_PERF_SEL_SE0_SH1_ORD_CNT             = 23,
GDS_PERF_SEL_SE0_SH1_2COMP_REQ           = 24,
GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID      = 25,
GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID      = 26,
GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD    = 27,
GDS_PERF_SEL_SE0_SH1_GDS_WR_OP           = 28,
GDS_PERF_SEL_SE0_SH1_GDS_RD_OP           = 29,
GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP         = 30,
GDS_PERF_SEL_SE0_SH1_GDS_REL_OP          = 31,
GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP       = 32,
GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP         = 33,
GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP        = 34,
GDS_PERF_SEL_SE1_SH0_NORET               = 35,
GDS_PERF_SEL_SE1_SH0_RET                 = 36,
GDS_PERF_SEL_SE1_SH0_ORD_CNT             = 37,
GDS_PERF_SEL_SE1_SH0_2COMP_REQ           = 38,
GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID      = 39,
GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID      = 40,
GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD    = 41,
GDS_PERF_SEL_SE1_SH0_GDS_WR_OP           = 42,
GDS_PERF_SEL_SE1_SH0_GDS_RD_OP           = 43,
GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP         = 44,
GDS_PERF_SEL_SE1_SH0_GDS_REL_OP          = 45,
GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP       = 46,
GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP         = 47,
GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP        = 48,
GDS_PERF_SEL_SE1_SH1_NORET               = 49,
GDS_PERF_SEL_SE1_SH1_RET                 = 50,
GDS_PERF_SEL_SE1_SH1_ORD_CNT             = 51,
GDS_PERF_SEL_SE1_SH1_2COMP_REQ           = 52,
GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID      = 53,
GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID      = 54,
GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD    = 55,
GDS_PERF_SEL_SE1_SH1_GDS_WR_OP           = 56,
GDS_PERF_SEL_SE1_SH1_GDS_RD_OP           = 57,
GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP         = 58,
GDS_PERF_SEL_SE1_SH1_GDS_REL_OP          = 59,
GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP       = 60,
GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP         = 61,
GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP        = 62,
GDS_PERF_SEL_SE2_SH0_NORET               = 63,
GDS_PERF_SEL_SE2_SH0_RET                 = 64,
GDS_PERF_SEL_SE2_SH0_ORD_CNT             = 65,
GDS_PERF_SEL_SE2_SH0_2COMP_REQ           = 66,
GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID      = 67,
GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID      = 68,
GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD    = 69,
GDS_PERF_SEL_SE2_SH0_GDS_WR_OP           = 70,
GDS_PERF_SEL_SE2_SH0_GDS_RD_OP           = 71,
GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP         = 72,
GDS_PERF_SEL_SE2_SH0_GDS_REL_OP          = 73,
GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP       = 74,
GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP         = 75,
GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP        = 76,
GDS_PERF_SEL_SE2_SH1_NORET               = 77,
GDS_PERF_SEL_SE2_SH1_RET                 = 78,
GDS_PERF_SEL_SE2_SH1_ORD_CNT             = 79,
GDS_PERF_SEL_SE2_SH1_2COMP_REQ           = 80,
GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID      = 81,
GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID      = 82,
GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD    = 83,
GDS_PERF_SEL_SE2_SH1_GDS_WR_OP           = 84,
GDS_PERF_SEL_SE2_SH1_GDS_RD_OP           = 85,
GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP         = 86,
GDS_PERF_SEL_SE2_SH1_GDS_REL_OP          = 87,
GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP       = 88,
GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP         = 89,
GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP        = 90,
GDS_PERF_SEL_SE3_SH0_NORET               = 91,
GDS_PERF_SEL_SE3_SH0_RET                 = 92,
GDS_PERF_SEL_SE3_SH0_ORD_CNT             = 93,
GDS_PERF_SEL_SE3_SH0_2COMP_REQ           = 94,
GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID      = 95,
GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID      = 96,
GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD    = 97,
GDS_PERF_SEL_SE3_SH0_GDS_WR_OP           = 98,
GDS_PERF_SEL_SE3_SH0_GDS_RD_OP           = 99,
GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP         = 100,
GDS_PERF_SEL_SE3_SH0_GDS_REL_OP          = 101,
GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP       = 102,
GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP         = 103,
GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP        = 104,
GDS_PERF_SEL_SE3_SH1_NORET               = 105,
GDS_PERF_SEL_SE3_SH1_RET                 = 106,
GDS_PERF_SEL_SE3_SH1_ORD_CNT             = 107,
GDS_PERF_SEL_SE3_SH1_2COMP_REQ           = 108,
GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID      = 109,
GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID      = 110,
GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD    = 111,
GDS_PERF_SEL_SE3_SH1_GDS_WR_OP           = 112,
GDS_PERF_SEL_SE3_SH1_GDS_RD_OP           = 113,
GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP         = 114,
GDS_PERF_SEL_SE3_SH1_GDS_REL_OP          = 115,
GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP       = 116,
GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP         = 117,
GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP        = 118,
GDS_PERF_SEL_GWS_RELEASED                = 119,
GDS_PERF_SEL_GWS_BYPASS                  = 120,
} GDS_PERFCOUNT_SELECT;

typedef enum GRBM_PERF_SEL {
GRBM_PERF_SEL_COUNT                      = 0x00000000,
GRBM_PERF_SEL_USER_DEFINED               = 0x00000001,
GRBM_PERF_SEL_GUI_ACTIVE                 = 0x00000002,
GRBM_PERF_SEL_CP_BUSY                    = 0x00000003,
GRBM_PERF_SEL_CP_COHER_BUSY              = 0x00000004,
GRBM_PERF_SEL_CP_DMA_BUSY                = 0x00000005,
GRBM_PERF_SEL_CB_BUSY                    = 0x00000006,
GRBM_PERF_SEL_DB_BUSY                    = 0x00000007,
GRBM_PERF_SEL_PA_BUSY                    = 0x00000008,
GRBM_PERF_SEL_SC_BUSY                    = 0x00000009,
GRBM_PERF_SEL_RESERVED_6                 = 0x0000000a,
GRBM_PERF_SEL_SPI_BUSY                   = 0x0000000b,
GRBM_PERF_SEL_SX_BUSY                    = 0x0000000c,
GRBM_PERF_SEL_TA_BUSY                    = 0x0000000d,
GRBM_PERF_SEL_CB_CLEAN                   = 0x0000000e,
GRBM_PERF_SEL_DB_CLEAN                   = 0x0000000f,
GRBM_PERF_SEL_RESERVED_5                 = 0x00000010,
GRBM_PERF_SEL_VGT_BUSY__GFX09            = 0x00000011,
GRBM_PERF_SEL_RESERVED_4                 = 0x00000012,
GRBM_PERF_SEL_RESERVED_3                 = 0x00000013,
GRBM_PERF_SEL_RESERVED_2                 = 0x00000014,
GRBM_PERF_SEL_RESERVED_1                 = 0x00000015,
GRBM_PERF_SEL_RESERVED_0                 = 0x00000016,
GRBM_PERF_SEL_IA_BUSY__GFX09             = 0x00000017,
GRBM_PERF_SEL_IA_NO_DMA_BUSY__GFX09      = 0x00000018,
GRBM_PERF_SEL_GDS_BUSY                   = 0x00000019,
GRBM_PERF_SEL_BCI_BUSY                   = 0x0000001a,
GRBM_PERF_SEL_RLC_BUSY                   = 0x0000001b,
GRBM_PERF_SEL_TC_BUSY__GFX09             = 0x0000001c,
GRBM_PERF_SEL_CPG_BUSY                   = 0x0000001d,
GRBM_PERF_SEL_CPC_BUSY                   = 0x0000001e,
GRBM_PERF_SEL_CPF_BUSY                   = 0x0000001f,
GRBM_PERF_SEL_WD_BUSY__GFX09             = 0x00000020,
GRBM_PERF_SEL_WD_NO_DMA_BUSY__GFX09      = 0x00000021,
GRBM_PERF_SEL_CPAXI_BUSY                 = 0x00000025,
} GRBM_PERF_SEL;

typedef enum GRBM_SE0_PERF_SEL {
GRBM_SE0_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE0_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE0_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE0_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE0_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE0_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE0_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE0_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE0_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE0_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE0_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE0_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE0_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE0_PERF_SEL_VGT_BUSY__GFX09        = 0x0000000d,
GRBM_SE0_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE0_PERF_SEL;

typedef enum GRBM_SE1_PERF_SEL {
GRBM_SE1_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE1_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE1_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE1_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE1_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE1_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE1_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE1_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE1_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE1_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE1_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE1_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE1_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE1_PERF_SEL_VGT_BUSY__GFX09        = 0x0000000d,
GRBM_SE1_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE1_PERF_SEL;

typedef enum GRBM_SE2_PERF_SEL {
GRBM_SE2_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE2_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE2_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE2_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE2_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE2_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE2_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE2_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE2_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE2_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE2_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE2_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE2_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE2_PERF_SEL_VGT_BUSY__GFX09        = 0x0000000d,
GRBM_SE2_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE2_PERF_SEL;

typedef enum GRBM_SE3_PERF_SEL {
GRBM_SE3_PERF_SEL_COUNT                  = 0x00000000,
GRBM_SE3_PERF_SEL_USER_DEFINED           = 0x00000001,
GRBM_SE3_PERF_SEL_CB_BUSY                = 0x00000002,
GRBM_SE3_PERF_SEL_DB_BUSY                = 0x00000003,
GRBM_SE3_PERF_SEL_SC_BUSY                = 0x00000004,
GRBM_SE3_PERF_SEL_RESERVED_1             = 0x00000005,
GRBM_SE3_PERF_SEL_SPI_BUSY               = 0x00000006,
GRBM_SE3_PERF_SEL_SX_BUSY                = 0x00000007,
GRBM_SE3_PERF_SEL_TA_BUSY                = 0x00000008,
GRBM_SE3_PERF_SEL_CB_CLEAN               = 0x00000009,
GRBM_SE3_PERF_SEL_DB_CLEAN               = 0x0000000a,
GRBM_SE3_PERF_SEL_RESERVED_0             = 0x0000000b,
GRBM_SE3_PERF_SEL_PA_BUSY                = 0x0000000c,
GRBM_SE3_PERF_SEL_VGT_BUSY__GFX09        = 0x0000000d,
GRBM_SE3_PERF_SEL_BCI_BUSY               = 0x0000000e,
} GRBM_SE3_PERF_SEL;

typedef enum GroupInterleave {
CONFIG_256B_GROUP                        = 0x00000000,
CONFIG_512B_GROUP                        = 0x00000001,
} GroupInterleave;

typedef enum IA_PERFCOUNT_SELECT {
ia_perf_dma_data_fifo_full               = 0x00000001,
ia_perf_MC_LAT_BIN_0                     = 0x00000007,
ia_perf_MC_LAT_BIN_1                     = 0x00000008,
ia_perf_MC_LAT_BIN_2                     = 0x00000009,
ia_perf_MC_LAT_BIN_3                     = 0x0000000a,
ia_perf_MC_LAT_BIN_4                     = 0x0000000b,
ia_perf_MC_LAT_BIN_5                     = 0x0000000c,
ia_perf_MC_LAT_BIN_6                     = 0x0000000d,
ia_perf_MC_LAT_BIN_7                     = 0x0000000e,
ia_perf_ia_busy                          = 0x0000000f,
ia_perf_ia_dma_return                    = 0x00000014,
ia_perf_shift_starved_pipe0_event        = 0x00000016,
ia_perf_shift_starved_pipe1_event        = 0x00000017,
ia_perf_utcl1_stall_utcl2_event          = 0x0000001f,
} IA_PERFCOUNT_SELECT;

typedef enum IH_PERF_SEL {
IH_PERF_SEL_CYCLE                        = 0x00000000,
IH_PERF_SEL_IDLE                         = 0x00000001,
IH_PERF_SEL_INPUT_IDLE                   = 0x00000002,
IH_PERF_SEL_MC_WR_IDLE                   = 0x00000009,
IH_PERF_SEL_MC_WR_COUNT                  = 0x0000000a,
IH_PERF_SEL_MC_WR_STALL                  = 0x0000000b,
IH_PERF_SEL_MC_WR_CLEAN_PENDING          = 0x0000000c,
IH_PERF_SEL_MC_WR_CLEAN_STALL            = 0x0000000d,
} IH_PERF_SEL;

typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID                  = 0x00000000,
IMG_DATA_FORMAT_8                        = 0x00000001,
IMG_DATA_FORMAT_16                       = 0x00000002,
IMG_DATA_FORMAT_8_8                      = 0x00000003,
IMG_DATA_FORMAT_32                       = 0x00000004,
IMG_DATA_FORMAT_16_16                    = 0x00000005,
IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
IMG_DATA_FORMAT_32_32                    = 0x0000000b,
IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
IMG_DATA_FORMAT_8_24                     = 0x00000014,
IMG_DATA_FORMAT_24_8                     = 0x00000015,
IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
IMG_DATA_FORMAT_8_AS_8_8_8_8__GFX09      = 0x00000017,
IMG_DATA_FORMAT_ETC2_RGB__GFX09          = 0x00000018,
IMG_DATA_FORMAT_ETC2_RGBA__GFX09         = 0x00000019,
IMG_DATA_FORMAT_ETC2_R__GFX09            = 0x0000001a,
IMG_DATA_FORMAT_ETC2_RG__GFX09           = 0x0000001b,
IMG_DATA_FORMAT_ETC2_RGBA1__GFX09        = 0x0000001c,
IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
IMG_DATA_FORMAT_BC1                      = 0x00000023,
IMG_DATA_FORMAT_BC2                      = 0x00000024,
IMG_DATA_FORMAT_BC3                      = 0x00000025,
IMG_DATA_FORMAT_BC4                      = 0x00000026,
IMG_DATA_FORMAT_BC5                      = 0x00000027,
IMG_DATA_FORMAT_BC6                      = 0x00000028,
IMG_DATA_FORMAT_BC7                      = 0x00000029,
IMG_DATA_FORMAT_16_AS_32_32__GFX09       = 0x0000002a,
IMG_DATA_FORMAT_16_AS_16_16_16_16__GFX09 = 0x0000002b,
IMG_DATA_FORMAT_16_AS_32_32_32_32__GFX09 = 0x0000002c,
IMG_DATA_FORMAT_FMASK__GFX09             = 0x0000002d,
IMG_DATA_FORMAT_ASTC_2D_LDR__GFX09       = 0x0000002e,
IMG_DATA_FORMAT_ASTC_2D_HDR__GFX09       = 0x0000002f,
IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB__GFX09  = 0x00000030,
IMG_DATA_FORMAT_4_4                      = 0x00000039,
IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
IMG_DATA_FORMAT_S8_16__GFX09             = 0x0000003b,
IMG_DATA_FORMAT_S8_32__GFX09             = 0x0000003c,
IMG_DATA_FORMAT_8_AS_32__GFX09           = 0x0000003d,
IMG_DATA_FORMAT_8_AS_32_32__GFX09        = 0x0000003e,
IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
} IMG_DATA_FORMAT;

typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM                     = 0x00000000,
IMG_NUM_FORMAT_SNORM                     = 0x00000001,
IMG_NUM_FORMAT_USCALED                   = 0x00000002,
IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
IMG_NUM_FORMAT_UINT                      = 0x00000004,
IMG_NUM_FORMAT_SINT                      = 0x00000005,
IMG_NUM_FORMAT_RESERVED_6__GFX09         = 0x00000006,
IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
IMG_NUM_FORMAT_SRGB                      = 0x00000009,
IMG_NUM_FORMAT_RESERVED_11__GFX09        = 0x0000000b,
IMG_NUM_FORMAT_RESERVED_12__GFX09        = 0x0000000c,
IMG_NUM_FORMAT_RESERVED_13__GFX09        = 0x0000000d,
IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
} IMG_NUM_FORMAT;

typedef enum IMG_NUM_FORMAT_ASTC_2D {
IMG_NUM_FORMAT_ASTC_2D_4x4__GFX09        = 0x00000000,
IMG_NUM_FORMAT_ASTC_2D_5x4__GFX09        = 0x00000001,
IMG_NUM_FORMAT_ASTC_2D_5x5__GFX09        = 0x00000002,
IMG_NUM_FORMAT_ASTC_2D_6x5__GFX09        = 0x00000003,
IMG_NUM_FORMAT_ASTC_2D_6x6__GFX09        = 0x00000004,
IMG_NUM_FORMAT_ASTC_2D_8x5__GFX09        = 0x00000005,
IMG_NUM_FORMAT_ASTC_2D_8x6__GFX09        = 0x00000006,
IMG_NUM_FORMAT_ASTC_2D_8x8__GFX09        = 0x00000007,
IMG_NUM_FORMAT_ASTC_2D_10x5__GFX09       = 0x00000008,
IMG_NUM_FORMAT_ASTC_2D_10x6__GFX09       = 0x00000009,
IMG_NUM_FORMAT_ASTC_2D_10x8__GFX09       = 0x0000000a,
IMG_NUM_FORMAT_ASTC_2D_10x10__GFX09      = 0x0000000b,
IMG_NUM_FORMAT_ASTC_2D_12x10__GFX09      = 0x0000000c,
IMG_NUM_FORMAT_ASTC_2D_12x12__GFX09      = 0x0000000d,
} IMG_NUM_FORMAT_ASTC_2D;

typedef enum IMG_NUM_FORMAT_ASTC_3D {
} IMG_NUM_FORMAT_ASTC_3D;

typedef enum IMG_NUM_FORMAT_FMASK {
IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
} IMG_NUM_FORMAT_FMASK;

typedef enum IMG_NUM_FORMAT_N_IN_16 {
} IMG_NUM_FORMAT_N_IN_16;

typedef enum MTYPE {
MTYPE_NC__GFX09                          = 0x00000000,
MTYPE_WC__GFX09                          = 0x00000001,
MTYPE_CC__GFX09                          = 0x00000002,
MTYPE_UC                                 = 0x00000003,
} MTYPE;

typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
} MacroTileAspect;

typedef enum MemArbMode {
} MemArbMode;

typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
} MicroTileMode;

typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
} MultiGPUTileSize;

typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
} NonDispTilingOrder;

typedef enum NumBanks {
ADDR_SURF_2_BANK                         = 0x00000000,
ADDR_SURF_4_BANK                         = 0x00000001,
ADDR_SURF_8_BANK                         = 0x00000002,
ADDR_SURF_16_BANK                        = 0x00000003,
} NumBanks;

typedef enum NumBanksConfig {
} NumBanksConfig;

typedef enum NumGPUs {
ADDR_CONFIG_1_GPU                        = 0x00000000,
ADDR_CONFIG_2_GPU                        = 0x00000001,
ADDR_CONFIG_4_GPU                        = 0x00000002,
} NumGPUs;

typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
} NumLowerPipes;

typedef enum NumMaxCompressedFragments {
} NumMaxCompressedFragments;

typedef enum NumPipes {
ADDR_CONFIG_1_PIPE                       = 0x00000000,
ADDR_CONFIG_2_PIPE                       = 0x00000001,
ADDR_CONFIG_4_PIPE                       = 0x00000002,
ADDR_CONFIG_8_PIPE                       = 0x00000003,
ADDR_CONFIG_16_PIPE                      = 0x00000004,
} NumPipes;

typedef enum NumRbPerShaderEngine {
} NumRbPerShaderEngine;

typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
} NumShaderEngines;

typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
} PERFMON_COUNTER_MODE;

typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF                     = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
} PERFMON_SPM_MODE;

typedef enum PerfCounter_Vals {
DB_PERF_SEL_SC_DB_tile_sends             = 0x00000000,
DB_PERF_SEL_SC_DB_tile_busy              = 0x00000001,
DB_PERF_SEL_SC_DB_tile_stalls            = 0x00000002,
DB_PERF_SEL_SC_DB_tile_events            = 0x00000003,
DB_PERF_SEL_SC_DB_tile_tiles             = 0x00000004,
DB_PERF_SEL_SC_DB_tile_covered           = 0x00000005,
DB_PERF_SEL_hiz_tc_read_starved          = 0x00000006,
DB_PERF_SEL_hiz_tc_write_stall           = 0x00000007,
DB_PERF_SEL_hiz_qtiles_culled__GFX09     = 0x00000008,
DB_PERF_SEL_his_qtiles_culled__GFX09     = 0x00000009,
DB_PERF_SEL_DB_SC_tile_sends             = 0x0000000a,
DB_PERF_SEL_DB_SC_tile_busy              = 0x0000000b,
DB_PERF_SEL_DB_SC_tile_stalls            = 0x0000000c,
DB_PERF_SEL_DB_SC_tile_df_stalls         = 0x0000000d,
DB_PERF_SEL_DB_SC_tile_tiles             = 0x0000000e,
DB_PERF_SEL_DB_SC_tile_culled            = 0x0000000f,
DB_PERF_SEL_DB_SC_tile_hier_kill         = 0x00000010,
DB_PERF_SEL_DB_SC_tile_fast_ops          = 0x00000011,
DB_PERF_SEL_DB_SC_tile_no_ops            = 0x00000012,
DB_PERF_SEL_DB_SC_tile_tile_rate         = 0x00000013,
DB_PERF_SEL_DB_SC_tile_ssaa_kill         = 0x00000014,
DB_PERF_SEL_DB_SC_tile_fast_z_ops        = 0x00000015,
DB_PERF_SEL_DB_SC_tile_fast_stencil_ops  = 0x00000016,
DB_PERF_SEL_SC_DB_quad_sends             = 0x00000017,
DB_PERF_SEL_SC_DB_quad_busy              = 0x00000018,
DB_PERF_SEL_SC_DB_quad_squads            = 0x00000019,
DB_PERF_SEL_SC_DB_quad_tiles             = 0x0000001a,
DB_PERF_SEL_SC_DB_quad_pixels            = 0x0000001b,
DB_PERF_SEL_SC_DB_quad_killed_tiles      = 0x0000001c,
DB_PERF_SEL_DB_SC_quad_sends             = 0x0000001d,
DB_PERF_SEL_DB_SC_quad_busy              = 0x0000001e,
DB_PERF_SEL_DB_SC_quad_stalls            = 0x0000001f,
DB_PERF_SEL_DB_SC_quad_tiles             = 0x00000020,
DB_PERF_SEL_DB_SC_quad_lit_quad          = 0x00000021,
DB_PERF_SEL_DB_CB_tile_sends             = 0x00000022,
DB_PERF_SEL_DB_CB_tile_busy              = 0x00000023,
DB_PERF_SEL_DB_CB_tile_stalls            = 0x00000024,
DB_PERF_SEL_SX_DB_quad_sends             = 0x00000025,
DB_PERF_SEL_SX_DB_quad_busy              = 0x00000026,
DB_PERF_SEL_SX_DB_quad_stalls            = 0x00000027,
DB_PERF_SEL_SX_DB_quad_quads             = 0x00000028,
DB_PERF_SEL_SX_DB_quad_pixels            = 0x00000029,
DB_PERF_SEL_SX_DB_quad_exports           = 0x0000002a,
DB_PERF_SEL_SH_quads_outstanding_sum     = 0x0000002b,
DB_PERF_SEL_DB_CB_lquad_sends            = 0x0000002c,
DB_PERF_SEL_DB_CB_lquad_busy             = 0x0000002d,
DB_PERF_SEL_DB_CB_lquad_stalls           = 0x0000002e,
DB_PERF_SEL_DB_CB_lquad_quads            = 0x0000002f,
DB_PERF_SEL_tile_rd_sends                = 0x00000030,
DB_PERF_SEL_mi_tile_rd_outstanding_sum   = 0x00000031,
DB_PERF_SEL_quad_rd_sends                = 0x00000032,
DB_PERF_SEL_quad_rd_busy                 = 0x00000033,
DB_PERF_SEL_quad_rd_mi_stall             = 0x00000034,
DB_PERF_SEL_quad_rd_rw_collision         = 0x00000035,
DB_PERF_SEL_quad_rd_tag_stall            = 0x00000036,
DB_PERF_SEL_quad_rd_32byte_reqs          = 0x00000037,
DB_PERF_SEL_quad_rd_panic                = 0x00000038,
DB_PERF_SEL_mi_quad_rd_outstanding_sum   = 0x00000039,
DB_PERF_SEL_quad_rdret_sends             = 0x0000003a,
DB_PERF_SEL_quad_rdret_busy              = 0x0000003b,
DB_PERF_SEL_tile_wr_sends                = 0x0000003c,
DB_PERF_SEL_tile_wr_acks                 = 0x0000003d,
DB_PERF_SEL_mi_tile_wr_outstanding_sum   = 0x0000003e,
DB_PERF_SEL_quad_wr_sends                = 0x0000003f,
DB_PERF_SEL_quad_wr_busy                 = 0x00000040,
DB_PERF_SEL_quad_wr_mi_stall             = 0x00000041,
DB_PERF_SEL_quad_wr_coherency_stall      = 0x00000042,
DB_PERF_SEL_quad_wr_acks                 = 0x00000043,
DB_PERF_SEL_mi_quad_wr_outstanding_sum   = 0x00000044,
DB_PERF_SEL_Tile_Cache_misses            = 0x00000045,
DB_PERF_SEL_Tile_Cache_hits              = 0x00000046,
DB_PERF_SEL_Tile_Cache_flushes           = 0x00000047,
DB_PERF_SEL_Tile_Cache_surface_stall     = 0x00000048,
DB_PERF_SEL_Tile_Cache_starves           = 0x00000049,
DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
DB_PERF_SEL_tcp_dispatcher_reads         = 0x0000004b,
DB_PERF_SEL_tcp_prefetcher_reads         = 0x0000004c,
DB_PERF_SEL_tcp_preloader_reads          = 0x0000004d,
DB_PERF_SEL_tcp_dispatcher_flushes       = 0x0000004e,
DB_PERF_SEL_tcp_prefetcher_flushes       = 0x0000004f,
DB_PERF_SEL_tcp_preloader_flushes        = 0x00000050,
DB_PERF_SEL_Depth_Tile_Cache_sends       = 0x00000051,
DB_PERF_SEL_Depth_Tile_Cache_busy        = 0x00000052,
DB_PERF_SEL_Depth_Tile_Cache_starves     = 0x00000053,
DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
DB_PERF_SEL_Depth_Tile_Cache_misses      = 0x00000056,
DB_PERF_SEL_Depth_Tile_Cache_hits        = 0x00000057,
DB_PERF_SEL_Depth_Tile_Cache_flushes     = 0x00000058,
DB_PERF_SEL_Depth_Tile_Cache_noop_tile   = 0x00000059,
DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
DB_PERF_SEL_Depth_Tile_Cache_event       = 0x0000005b,
DB_PERF_SEL_Depth_Tile_Cache_tile_frees  = 0x0000005c,
DB_PERF_SEL_Depth_Tile_Cache_data_frees  = 0x0000005d,
DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
DB_PERF_SEL_Stencil_Cache_misses         = 0x0000005f,
DB_PERF_SEL_Stencil_Cache_hits           = 0x00000060,
DB_PERF_SEL_Stencil_Cache_flushes        = 0x00000061,
DB_PERF_SEL_Stencil_Cache_starves        = 0x00000062,
DB_PERF_SEL_Stencil_Cache_frees          = 0x00000063,
DB_PERF_SEL_Z_Cache_separate_Z_misses    = 0x00000064,
DB_PERF_SEL_Z_Cache_separate_Z_hits      = 0x00000065,
DB_PERF_SEL_Z_Cache_separate_Z_flushes   = 0x00000066,
DB_PERF_SEL_Z_Cache_separate_Z_starves   = 0x00000067,
DB_PERF_SEL_Z_Cache_pmask_misses         = 0x00000068,
DB_PERF_SEL_Z_Cache_pmask_hits           = 0x00000069,
DB_PERF_SEL_Z_Cache_pmask_flushes        = 0x0000006a,
DB_PERF_SEL_Z_Cache_pmask_starves        = 0x0000006b,
DB_PERF_SEL_Z_Cache_frees                = 0x0000006c,
DB_PERF_SEL_Plane_Cache_misses           = 0x0000006d,
DB_PERF_SEL_Plane_Cache_hits             = 0x0000006e,
DB_PERF_SEL_Plane_Cache_flushes          = 0x0000006f,
DB_PERF_SEL_Plane_Cache_starves          = 0x00000070,
DB_PERF_SEL_Plane_Cache_frees            = 0x00000071,
DB_PERF_SEL_flush_expanded_stencil       = 0x00000072,
DB_PERF_SEL_flush_compressed_stencil     = 0x00000073,
DB_PERF_SEL_flush_single_stencil         = 0x00000074,
DB_PERF_SEL_planes_flushed               = 0x00000075,
DB_PERF_SEL_flush_1plane                 = 0x00000076,
DB_PERF_SEL_flush_2plane                 = 0x00000077,
DB_PERF_SEL_flush_3plane                 = 0x00000078,
DB_PERF_SEL_flush_4plane                 = 0x00000079,
DB_PERF_SEL_flush_5plane                 = 0x0000007a,
DB_PERF_SEL_flush_6plane                 = 0x0000007b,
DB_PERF_SEL_flush_7plane                 = 0x0000007c,
DB_PERF_SEL_flush_8plane                 = 0x0000007d,
DB_PERF_SEL_flush_9plane                 = 0x0000007e,
DB_PERF_SEL_flush_10plane                = 0x0000007f,
DB_PERF_SEL_flush_11plane                = 0x00000080,
DB_PERF_SEL_flush_12plane                = 0x00000081,
DB_PERF_SEL_flush_13plane                = 0x00000082,
DB_PERF_SEL_flush_14plane                = 0x00000083,
DB_PERF_SEL_flush_15plane                = 0x00000084,
DB_PERF_SEL_flush_16plane                = 0x00000085,
DB_PERF_SEL_flush_expanded_z             = 0x00000086,
DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
DB_PERF_SEL_reZ_waiting_for_postZ_done   = 0x00000088,
DB_PERF_SEL_dk_tile_sends                = 0x00000089,
DB_PERF_SEL_dk_tile_busy                 = 0x0000008a,
DB_PERF_SEL_dk_tile_quad_starves         = 0x0000008b,
DB_PERF_SEL_dk_tile_stalls               = 0x0000008c,
DB_PERF_SEL_dk_squad_sends               = 0x0000008d,
DB_PERF_SEL_dk_squad_busy                = 0x0000008e,
DB_PERF_SEL_dk_squad_stalls              = 0x0000008f,
DB_PERF_SEL_Op_Pipe_Busy                 = 0x00000090,
DB_PERF_SEL_Op_Pipe_MC_Read_stall        = 0x00000091,
DB_PERF_SEL_qc_busy                      = 0x00000092,
DB_PERF_SEL_qc_xfc                       = 0x00000093,
DB_PERF_SEL_qc_conflicts                 = 0x00000094,
DB_PERF_SEL_qc_full_stall                = 0x00000095,
DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
DB_PERF_SEL_tsc_insert_summarize_stall   = 0x00000098,
DB_PERF_SEL_tl_busy                      = 0x00000099,
DB_PERF_SEL_tl_dtc_read_starved          = 0x0000009a,
DB_PERF_SEL_tl_z_fetch_stall             = 0x0000009b,
DB_PERF_SEL_tl_stencil_stall             = 0x0000009c,
DB_PERF_SEL_tl_z_decompress_stall        = 0x0000009d,
DB_PERF_SEL_tl_stencil_locked_stall      = 0x0000009e,
DB_PERF_SEL_tl_events                    = 0x0000009f,
DB_PERF_SEL_tl_summarize_squads          = 0x000000a0,
DB_PERF_SEL_tl_flush_expand_squads       = 0x000000a1,
DB_PERF_SEL_tl_expand_squads             = 0x000000a2,
DB_PERF_SEL_tl_preZ_squads               = 0x000000a3,
DB_PERF_SEL_tl_postZ_squads              = 0x000000a4,
DB_PERF_SEL_tl_preZ_noop_squads          = 0x000000a5,
DB_PERF_SEL_tl_postZ_noop_squads         = 0x000000a6,
DB_PERF_SEL_tl_tile_ops                  = 0x000000a7,
DB_PERF_SEL_tl_in_xfc                    = 0x000000a8,
DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
DB_PERF_SEL_tl_in_fast_z_stall           = 0x000000aa,
DB_PERF_SEL_tl_out_xfc                   = 0x000000ab,
DB_PERF_SEL_tl_out_squads                = 0x000000ac,
DB_PERF_SEL_zf_plane_multicycle          = 0x000000ad,
DB_PERF_SEL_PostZ_Samples_passing_Z      = 0x000000ae,
DB_PERF_SEL_PostZ_Samples_failing_Z      = 0x000000af,
DB_PERF_SEL_PostZ_Samples_failing_S      = 0x000000b0,
DB_PERF_SEL_PreZ_Samples_passing_Z       = 0x000000b1,
DB_PERF_SEL_PreZ_Samples_failing_Z       = 0x000000b2,
DB_PERF_SEL_PreZ_Samples_failing_S       = 0x000000b3,
DB_PERF_SEL_ts_tc_update_stall           = 0x000000b4,
DB_PERF_SEL_sc_kick_start                = 0x000000b5,
DB_PERF_SEL_sc_kick_end                  = 0x000000b6,
DB_PERF_SEL_clock_reg_active             = 0x000000b7,
DB_PERF_SEL_clock_main_active            = 0x000000b8,
DB_PERF_SEL_clock_mem_export_active      = 0x000000b9,
DB_PERF_SEL_esr_ps_out_busy              = 0x000000ba,
DB_PERF_SEL_esr_ps_lqf_busy              = 0x000000bb,
DB_PERF_SEL_esr_ps_lqf_stall             = 0x000000bc,
DB_PERF_SEL_etr_out_send                 = 0x000000bd,
DB_PERF_SEL_etr_out_busy                 = 0x000000be,
DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
DB_PERF_SEL_etr_out_cb_tile_stall        = 0x000000c0,
DB_PERF_SEL_etr_out_esr_stall            = 0x000000c1,
DB_PERF_SEL_esr_ps_sqq_busy              = 0x000000c2,
DB_PERF_SEL_esr_ps_sqq_stall             = 0x000000c3,
DB_PERF_SEL_esr_eot_fwd_busy             = 0x000000c4,
DB_PERF_SEL_esr_eot_fwd_holding_squad    = 0x000000c5,
DB_PERF_SEL_esr_eot_fwd_forward          = 0x000000c6,
DB_PERF_SEL_esr_sqq_zi_busy              = 0x000000c7,
DB_PERF_SEL_esr_sqq_zi_stall             = 0x000000c8,
DB_PERF_SEL_postzl_sq_pt_busy            = 0x000000c9,
DB_PERF_SEL_postzl_sq_pt_stall           = 0x000000ca,
DB_PERF_SEL_postzl_se_busy               = 0x000000cb,
DB_PERF_SEL_postzl_se_stall              = 0x000000cc,
DB_PERF_SEL_postzl_partial_launch        = 0x000000cd,
DB_PERF_SEL_postzl_full_launch           = 0x000000ce,
DB_PERF_SEL_postzl_partial_waiting       = 0x000000cf,
DB_PERF_SEL_postzl_tile_mem_stall        = 0x000000d0,
DB_PERF_SEL_postzl_tile_init_stall       = 0x000000d1,
DB_PEFF_SEL_prezl_tile_mem_stall__GFX09  = 0x000000d2,
DB_PERF_SEL_prezl_tile_init_stall        = 0x000000d3,
DB_PERF_SEL_dtt_sm_clash_stall           = 0x000000d4,
DB_PERF_SEL_dtt_sm_slot_stall            = 0x000000d5,
DB_PERF_SEL_dtt_sm_miss_stall            = 0x000000d6,
DB_PERF_SEL_mi_rdreq_busy                = 0x000000d7,
DB_PERF_SEL_mi_rdreq_stall               = 0x000000d8,
DB_PERF_SEL_mi_wrreq_busy                = 0x000000d9,
DB_PERF_SEL_mi_wrreq_stall               = 0x000000da,
DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
DB_PERF_SEL_dkg_tile_rate_tile           = 0x000000dc,
DB_PERF_SEL_prezl_src_in_sends           = 0x000000dd,
DB_PERF_SEL_prezl_src_in_stall           = 0x000000de,
DB_PERF_SEL_prezl_src_in_squads          = 0x000000df,
DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
DB_PERF_SEL_prezl_src_in_tile_rate       = 0x000000e1,
DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
DB_PERF_SEL_prezl_src_out_stall          = 0x000000e3,
DB_PERF_SEL_postzl_src_in_sends          = 0x000000e4,
DB_PERF_SEL_postzl_src_in_stall          = 0x000000e5,
DB_PERF_SEL_postzl_src_in_squads         = 0x000000e6,
DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
DB_PERF_SEL_postzl_src_in_tile_rate      = 0x000000e8,
DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
DB_PERF_SEL_postzl_src_out_stall         = 0x000000ea,
DB_PERF_SEL_esr_ps_src_in_sends          = 0x000000eb,
DB_PERF_SEL_esr_ps_src_in_stall          = 0x000000ec,
DB_PERF_SEL_esr_ps_src_in_squads         = 0x000000ed,
DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
DB_PERF_SEL_esr_ps_src_in_tile_rate      = 0x000000ef,
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
DB_PERF_SEL_esr_ps_src_out_stall         = 0x000000f2,
DB_PERF_SEL_depth_bounds_qtiles_culled__GFX09 = 0x000000f3,
DB_PERF_SEL_PreZ_Samples_failing_DB      = 0x000000f4,
DB_PERF_SEL_PostZ_Samples_failing_DB     = 0x000000f5,
DB_PERF_SEL_flush_compressed             = 0x000000f6,
DB_PERF_SEL_flush_plane_le4              = 0x000000f7,
DB_PERF_SEL_tiles_z_fully_summarized     = 0x000000f8,
DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
DB_PERF_SEL_tiles_z_clear_on_expclear    = 0x000000fa,
DB_PERF_SEL_tiles_s_clear_on_expclear    = 0x000000fb,
DB_PERF_SEL_tiles_decomp_on_expclear     = 0x000000fc,
DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
DB_PERF_SEL_Op_Pipe_Prez_Busy            = 0x000000fe,
DB_PERF_SEL_Op_Pipe_Postz_Busy           = 0x000000ff,
DB_PERF_SEL_di_dt_stall                  = 0x00000100,
DB_PERF_SEL_DB_SC_quad_double_quad__GFX09 = 0x00000101,
DB_PERF_SEL_SX_DB_quad_export_quads__GFX09 = 0x00000102,
DB_PERF_SEL_SX_DB_quad_double_format__GFX09 = 0x00000103,
DB_PERF_SEL_SX_DB_quad_fast_format__GFX09 = 0x00000104,
DB_PERF_SEL_SX_DB_quad_slow_format__GFX09 = 0x00000105,
DB_PERF_SEL_DB_CB_lquad_export_quads     = 0x00000106,
DB_PERF_SEL_DB_CB_lquad_double_format    = 0x00000107,
DB_PERF_SEL_DB_CB_lquad_fast_format      = 0x00000108,
DB_PERF_SEL_DB_CB_lquad_slow_format      = 0x00000109,
DB_PERF_SEL_SC_DB_quad_quads             = 0x00000143,
DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000147,
} PerfCounter_Vals;

typedef enum PipeConfig {
ADDR_SURF_P2                             = 0x00000000,
ADDR_SURF_P2_RESERVED0                   = 0x00000001,
ADDR_SURF_P2_RESERVED1                   = 0x00000002,
ADDR_SURF_P2_RESERVED2                   = 0x00000003,
ADDR_SURF_P4_8x16                        = 0x00000004,
ADDR_SURF_P4_16x16                       = 0x00000005,
ADDR_SURF_P4_16x32                       = 0x00000006,
ADDR_SURF_P4_32x32                       = 0x00000007,
ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
ADDR_SURF_P16_32x32_16x16                = 0x00000011,
} PipeConfig;

typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
} PipeInterleaveSize;

typedef enum PipeTiling {
CONFIG_1_PIPE                            = 0x00000000,
CONFIG_2_PIPE                            = 0x00000001,
CONFIG_4_PIPE                            = 0x00000002,
CONFIG_8_PIPE                            = 0x00000003,
} PipeTiling;

typedef enum PixelPipeCounterId {
PIXEL_PIPE_OCCLUSION_COUNT_0             = 0x00000000,
PIXEL_PIPE_OCCLUSION_COUNT_1             = 0x00000001,
PIXEL_PIPE_OCCLUSION_COUNT_2             = 0x00000002,
PIXEL_PIPE_OCCLUSION_COUNT_3             = 0x00000003,
PIXEL_PIPE_SCREEN_MIN_EXTENTS_0          = 0x00000004,
PIXEL_PIPE_SCREEN_MAX_EXTENTS_0          = 0x00000005,
PIXEL_PIPE_SCREEN_MIN_EXTENTS_1          = 0x00000006,
PIXEL_PIPE_SCREEN_MAX_EXTENTS_1          = 0x00000007,
} PixelPipeCounterId;

typedef enum PixelPipeStride {
PIXEL_PIPE_STRIDE_32_BITS                = 0x00000000,
PIXEL_PIPE_STRIDE_64_BITS                = 0x00000001,
PIXEL_PIPE_STRIDE_128_BITS               = 0x00000002,
PIXEL_PIPE_STRIDE_256_BITS               = 0x00000003,
} PixelPipeStride;

typedef enum PkrMap {
RASTER_CONFIG_PKR_MAP_0                  = 0x00000000,
RASTER_CONFIG_PKR_MAP_1                  = 0x00000001,
RASTER_CONFIG_PKR_MAP_2                  = 0x00000002,
RASTER_CONFIG_PKR_MAP_3                  = 0x00000003,
} PkrMap;

typedef enum PkrXsel {
RASTER_CONFIG_PKR_XSEL_0                 = 0x00000000,
RASTER_CONFIG_PKR_XSEL_1                 = 0x00000001,
RASTER_CONFIG_PKR_XSEL_2                 = 0x00000002,
RASTER_CONFIG_PKR_XSEL_3                 = 0x00000003,
} PkrXsel;

typedef enum PkrXsel2 {
RASTER_CONFIG_PKR_XSEL2_0                = 0x00000000,
RASTER_CONFIG_PKR_XSEL2_1                = 0x00000001,
RASTER_CONFIG_PKR_XSEL2_2                = 0x00000002,
RASTER_CONFIG_PKR_XSEL2_3                = 0x00000003,
} PkrXsel2;

typedef enum PkrYsel {
RASTER_CONFIG_PKR_YSEL_0                 = 0x00000000,
RASTER_CONFIG_PKR_YSEL_1                 = 0x00000001,
RASTER_CONFIG_PKR_YSEL_2                 = 0x00000002,
RASTER_CONFIG_PKR_YSEL_3                 = 0x00000003,
} PkrYsel;

typedef enum QuadExportFormat {
EXPORT_UNUSED                            = 0x00000000,
EXPORT_32_R                              = 0x00000001,
EXPORT_32_GR                             = 0x00000002,
EXPORT_32_AR                             = 0x00000003,
EXPORT_FP16_ABGR                         = 0x00000004,
EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
EXPORT_SIGNED16_ABGR                     = 0x00000006,
EXPORT_32_ABGR                           = 0x00000007,
EXPORT_32BPP_8PIX                        = 0x00000008,
EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
} QuadExportFormat;

typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR                     = 0x00000000,
EXPORT_4P_16BPC_ABGR                     = 0x00000001,
EXPORT_4P_32BPC_GR                       = 0x00000002,
EXPORT_4P_32BPC_AR                       = 0x00000003,
EXPORT_2P_32BPC_ABGR                     = 0x00000004,
EXPORT_8P_32BPC_R                        = 0x00000005,
} QuadExportFormatOld;

typedef enum RMIPerfSel {
RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3    = 0x00000100,
} RMIPerfSel;

typedef enum RMI_CID {
} RMI_CID;

typedef enum RbMap {
RASTER_CONFIG_RB_MAP_0                   = 0x00000000,
RASTER_CONFIG_RB_MAP_1                   = 0x00000001,
RASTER_CONFIG_RB_MAP_2                   = 0x00000002,
RASTER_CONFIG_RB_MAP_3                   = 0x00000003,
} RbMap;

typedef enum RbXsel {
RASTER_CONFIG_RB_XSEL_0                  = 0x00000000,
RASTER_CONFIG_RB_XSEL_1                  = 0x00000001,
} RbXsel;

typedef enum RbXsel2 {
RASTER_CONFIG_RB_XSEL2_0                 = 0x00000000,
RASTER_CONFIG_RB_XSEL2_1                 = 0x00000001,
RASTER_CONFIG_RB_XSEL2_2                 = 0x00000002,
RASTER_CONFIG_RB_XSEL2_3                 = 0x00000003,
} RbXsel2;

typedef enum RbYsel {
RASTER_CONFIG_RB_YSEL_0                  = 0x00000000,
RASTER_CONFIG_RB_YSEL_1                  = 0x00000001,
} RbYsel;

typedef enum ReadSize {
READ_256_BITS                            = 0x00000000,
READ_512_BITS                            = 0x00000001,
} ReadSize;

typedef enum RingCounterControl {
COUNTER_RING_SPLIT                       = 0x00000000,
COUNTER_RING_0                           = 0x00000001,
COUNTER_RING_1                           = 0x00000002,
} RingCounterControl;

typedef enum RoundMode {
ROUND_BY_HALF                            = 0x00000000,
ROUND_TRUNCATE                           = 0x00000001,
} RoundMode;

typedef enum RowSize {
ADDR_CONFIG_1KB_ROW                      = 0x00000000,
ADDR_CONFIG_2KB_ROW                      = 0x00000001,
ADDR_CONFIG_4KB_ROW                      = 0x00000002,
} RowSize;

typedef enum RowTiling {
CONFIG_1KB_ROW                           = 0x00000000,
CONFIG_2KB_ROW                           = 0x00000001,
CONFIG_4KB_ROW                           = 0x00000002,
CONFIG_8KB_ROW                           = 0x00000003,
CONFIG_1KB_ROW_OPT                       = 0x00000004,
CONFIG_2KB_ROW_OPT                       = 0x00000005,
CONFIG_4KB_ROW_OPT                       = 0x00000006,
CONFIG_8KB_ROW_OPT                       = 0x00000007,
} RowTiling;

typedef enum SC_PERFCNT_SEL {
SC_SRPS_WINDOW_VALID                     = 0x00000000,
SC_PSSW_WINDOW_VALID                     = 0x00000001,
SC_TPQZ_WINDOW_VALID                     = 0x00000002,
SC_QZQP_WINDOW_VALID                     = 0x00000003,
SC_TRPK_WINDOW_VALID                     = 0x00000004,
SC_SRPS_WINDOW_VALID_BUSY                = 0x00000005,
SC_PSSW_WINDOW_VALID_BUSY                = 0x00000006,
SC_TPQZ_WINDOW_VALID_BUSY                = 0x00000007,
SC_QZQP_WINDOW_VALID_BUSY                = 0x00000008,
SC_TRPK_WINDOW_VALID_BUSY                = 0x00000009,
SC_STARVED_BY_PA                         = 0x0000000a,
SC_STALLED_BY_PRIMFIFO                   = 0x0000000b,
SC_STALLED_BY_DB_TILE                    = 0x0000000c,
SC_STARVED_BY_DB_TILE                    = 0x0000000d,
SC_STALLED_BY_TILEORDERFIFO              = 0x0000000e,
SC_STALLED_BY_TILEFIFO                   = 0x0000000f,
SC_STALLED_BY_DB_QUAD                    = 0x00000010,
SC_STARVED_BY_DB_QUAD                    = 0x00000011,
SC_STALLED_BY_QUADFIFO                   = 0x00000012,
SC_STALLED_BY_BCI                        = 0x00000013,
SC_STALLED_BY_SPI                        = 0x00000014,
SC_SCISSOR_DISCARD                       = 0x00000015,
SC_BB_DISCARD                            = 0x00000016,
SC_SUPERTILE_COUNT                       = 0x00000017,
SC_SUPERTILE_PER_PRIM_H0                 = 0x00000018,
SC_SUPERTILE_PER_PRIM_H1                 = 0x00000019,
SC_SUPERTILE_PER_PRIM_H2                 = 0x0000001a,
SC_SUPERTILE_PER_PRIM_H3                 = 0x0000001b,
SC_SUPERTILE_PER_PRIM_H4                 = 0x0000001c,
SC_SUPERTILE_PER_PRIM_H5                 = 0x0000001d,
SC_SUPERTILE_PER_PRIM_H6                 = 0x0000001e,
SC_SUPERTILE_PER_PRIM_H7                 = 0x0000001f,
SC_SUPERTILE_PER_PRIM_H8                 = 0x00000020,
SC_SUPERTILE_PER_PRIM_H9                 = 0x00000021,
SC_SUPERTILE_PER_PRIM_H10                = 0x00000022,
SC_SUPERTILE_PER_PRIM_H11                = 0x00000023,
SC_SUPERTILE_PER_PRIM_H12                = 0x00000024,
SC_SUPERTILE_PER_PRIM_H13                = 0x00000025,
SC_SUPERTILE_PER_PRIM_H14                = 0x00000026,
SC_SUPERTILE_PER_PRIM_H15                = 0x00000027,
SC_SUPERTILE_PER_PRIM_H16                = 0x00000028,
SC_TILE_PER_PRIM_H0                      = 0x00000029,
SC_TILE_PER_PRIM_H1                      = 0x0000002a,
SC_TILE_PER_PRIM_H2                      = 0x0000002b,
SC_TILE_PER_PRIM_H3                      = 0x0000002c,
SC_TILE_PER_PRIM_H4                      = 0x0000002d,
SC_TILE_PER_PRIM_H5                      = 0x0000002e,
SC_TILE_PER_PRIM_H6                      = 0x0000002f,
SC_TILE_PER_PRIM_H7                      = 0x00000030,
SC_TILE_PER_PRIM_H8                      = 0x00000031,
SC_TILE_PER_PRIM_H9                      = 0x00000032,
SC_TILE_PER_PRIM_H10                     = 0x00000033,
SC_TILE_PER_PRIM_H11                     = 0x00000034,
SC_TILE_PER_PRIM_H12                     = 0x00000035,
SC_TILE_PER_PRIM_H13                     = 0x00000036,
SC_TILE_PER_PRIM_H14                     = 0x00000037,
SC_TILE_PER_PRIM_H15                     = 0x00000038,
SC_TILE_PER_PRIM_H16                     = 0x00000039,
SC_TILE_PER_SUPERTILE_H0                 = 0x0000003a,
SC_TILE_PER_SUPERTILE_H1                 = 0x0000003b,
SC_TILE_PER_SUPERTILE_H2                 = 0x0000003c,
SC_TILE_PER_SUPERTILE_H3                 = 0x0000003d,
SC_TILE_PER_SUPERTILE_H4                 = 0x0000003e,
SC_TILE_PER_SUPERTILE_H5                 = 0x0000003f,
SC_TILE_PER_SUPERTILE_H6                 = 0x00000040,
SC_TILE_PER_SUPERTILE_H7                 = 0x00000041,
SC_TILE_PER_SUPERTILE_H8                 = 0x00000042,
SC_TILE_PER_SUPERTILE_H9                 = 0x00000043,
SC_TILE_PER_SUPERTILE_H10                = 0x00000044,
SC_TILE_PER_SUPERTILE_H11                = 0x00000045,
SC_TILE_PER_SUPERTILE_H12                = 0x00000046,
SC_TILE_PER_SUPERTILE_H13                = 0x00000047,
SC_TILE_PER_SUPERTILE_H14                = 0x00000048,
SC_TILE_PER_SUPERTILE_H15                = 0x00000049,
SC_TILE_PER_SUPERTILE_H16                = 0x0000004a,
SC_TILE_PICKED_H1                        = 0x0000004b,
SC_TILE_PICKED_H2                        = 0x0000004c,
SC_TILE_PICKED_H3                        = 0x0000004d,
SC_TILE_PICKED_H4                        = 0x0000004e,
SC_QZ0_TILE_COUNT                        = 0x0000004f,
SC_QZ1_TILE_COUNT                        = 0x00000050,
SC_QZ2_TILE_COUNT                        = 0x00000051,
SC_QZ3_TILE_COUNT                        = 0x00000052,
SC_QZ0_TILE_COVERED_COUNT                = 0x00000053,
SC_QZ1_TILE_COVERED_COUNT                = 0x00000054,
SC_QZ2_TILE_COVERED_COUNT                = 0x00000055,
SC_QZ3_TILE_COVERED_COUNT                = 0x00000056,
SC_QZ0_TILE_NOT_COVERED_COUNT            = 0x00000057,
SC_QZ1_TILE_NOT_COVERED_COUNT            = 0x00000058,
SC_QZ2_TILE_NOT_COVERED_COUNT            = 0x00000059,
SC_QZ3_TILE_NOT_COVERED_COUNT            = 0x0000005a,
SC_QZ0_QUAD_PER_TILE_H0                  = 0x0000005b,
SC_QZ0_QUAD_PER_TILE_H1                  = 0x0000005c,
SC_QZ0_QUAD_PER_TILE_H2                  = 0x0000005d,
SC_QZ0_QUAD_PER_TILE_H3                  = 0x0000005e,
SC_QZ0_QUAD_PER_TILE_H4                  = 0x0000005f,
SC_QZ0_QUAD_PER_TILE_H5                  = 0x00000060,
SC_QZ0_QUAD_PER_TILE_H6                  = 0x00000061,
SC_QZ0_QUAD_PER_TILE_H7                  = 0x00000062,
SC_QZ0_QUAD_PER_TILE_H8                  = 0x00000063,
SC_QZ0_QUAD_PER_TILE_H9                  = 0x00000064,
SC_QZ0_QUAD_PER_TILE_H10                 = 0x00000065,
SC_QZ0_QUAD_PER_TILE_H11                 = 0x00000066,
SC_QZ0_QUAD_PER_TILE_H12                 = 0x00000067,
SC_QZ0_QUAD_PER_TILE_H13                 = 0x00000068,
SC_QZ0_QUAD_PER_TILE_H14                 = 0x00000069,
SC_QZ0_QUAD_PER_TILE_H15                 = 0x0000006a,
SC_QZ0_QUAD_PER_TILE_H16                 = 0x0000006b,
SC_QZ1_QUAD_PER_TILE_H0                  = 0x0000006c,
SC_QZ1_QUAD_PER_TILE_H1                  = 0x0000006d,
SC_QZ1_QUAD_PER_TILE_H2                  = 0x0000006e,
SC_QZ1_QUAD_PER_TILE_H3                  = 0x0000006f,
SC_QZ1_QUAD_PER_TILE_H4                  = 0x00000070,
SC_QZ1_QUAD_PER_TILE_H5                  = 0x00000071,
SC_QZ1_QUAD_PER_TILE_H6                  = 0x00000072,
SC_QZ1_QUAD_PER_TILE_H7                  = 0x00000073,
SC_QZ1_QUAD_PER_TILE_H8                  = 0x00000074,
SC_QZ1_QUAD_PER_TILE_H9                  = 0x00000075,
SC_QZ1_QUAD_PER_TILE_H10                 = 0x00000076,
SC_QZ1_QUAD_PER_TILE_H11                 = 0x00000077,
SC_QZ1_QUAD_PER_TILE_H12                 = 0x00000078,
SC_QZ1_QUAD_PER_TILE_H13                 = 0x00000079,
SC_QZ1_QUAD_PER_TILE_H14                 = 0x0000007a,
SC_QZ1_QUAD_PER_TILE_H15                 = 0x0000007b,
SC_QZ1_QUAD_PER_TILE_H16                 = 0x0000007c,
SC_QZ2_QUAD_PER_TILE_H0                  = 0x0000007d,
SC_QZ2_QUAD_PER_TILE_H1                  = 0x0000007e,
SC_QZ2_QUAD_PER_TILE_H2                  = 0x0000007f,
SC_QZ2_QUAD_PER_TILE_H3                  = 0x00000080,
SC_QZ2_QUAD_PER_TILE_H4                  = 0x00000081,
SC_QZ2_QUAD_PER_TILE_H5                  = 0x00000082,
SC_QZ2_QUAD_PER_TILE_H6                  = 0x00000083,
SC_QZ2_QUAD_PER_TILE_H7                  = 0x00000084,
SC_QZ2_QUAD_PER_TILE_H8                  = 0x00000085,
SC_QZ2_QUAD_PER_TILE_H9                  = 0x00000086,
SC_QZ2_QUAD_PER_TILE_H10                 = 0x00000087,
SC_QZ2_QUAD_PER_TILE_H11                 = 0x00000088,
SC_QZ2_QUAD_PER_TILE_H12                 = 0x00000089,
SC_QZ2_QUAD_PER_TILE_H13                 = 0x0000008a,
SC_QZ2_QUAD_PER_TILE_H14                 = 0x0000008b,
SC_QZ2_QUAD_PER_TILE_H15                 = 0x0000008c,
SC_QZ2_QUAD_PER_TILE_H16                 = 0x0000008d,
SC_QZ3_QUAD_PER_TILE_H0                  = 0x0000008e,
SC_QZ3_QUAD_PER_TILE_H1                  = 0x0000008f,
SC_QZ3_QUAD_PER_TILE_H2                  = 0x00000090,
SC_QZ3_QUAD_PER_TILE_H3                  = 0x00000091,
SC_QZ3_QUAD_PER_TILE_H4                  = 0x00000092,
SC_QZ3_QUAD_PER_TILE_H5                  = 0x00000093,
SC_QZ3_QUAD_PER_TILE_H6                  = 0x00000094,
SC_QZ3_QUAD_PER_TILE_H7                  = 0x00000095,
SC_QZ3_QUAD_PER_TILE_H8                  = 0x00000096,
SC_QZ3_QUAD_PER_TILE_H9                  = 0x00000097,
SC_QZ3_QUAD_PER_TILE_H10                 = 0x00000098,
SC_QZ3_QUAD_PER_TILE_H11                 = 0x00000099,
SC_QZ3_QUAD_PER_TILE_H12                 = 0x0000009a,
SC_QZ3_QUAD_PER_TILE_H13                 = 0x0000009b,
SC_QZ3_QUAD_PER_TILE_H14                 = 0x0000009c,
SC_QZ3_QUAD_PER_TILE_H15                 = 0x0000009d,
SC_QZ3_QUAD_PER_TILE_H16                 = 0x0000009e,
SC_QZ0_QUAD_COUNT                        = 0x0000009f,
SC_QZ1_QUAD_COUNT                        = 0x000000a0,
SC_QZ2_QUAD_COUNT                        = 0x000000a1,
SC_QZ3_QUAD_COUNT                        = 0x000000a2,
SC_P0_HIZ_TILE_COUNT                     = 0x000000a3,
SC_P1_HIZ_TILE_COUNT                     = 0x000000a4,
SC_P2_HIZ_TILE_COUNT                     = 0x000000a5,
SC_P3_HIZ_TILE_COUNT                     = 0x000000a6,
SC_P0_HIZ_QUAD_PER_TILE_H0               = 0x000000a7,
SC_P0_HIZ_QUAD_PER_TILE_H1               = 0x000000a8,
SC_P0_HIZ_QUAD_PER_TILE_H2               = 0x000000a9,
SC_P0_HIZ_QUAD_PER_TILE_H3               = 0x000000aa,
SC_P0_HIZ_QUAD_PER_TILE_H4               = 0x000000ab,
SC_P0_HIZ_QUAD_PER_TILE_H5               = 0x000000ac,
SC_P0_HIZ_QUAD_PER_TILE_H6               = 0x000000ad,
SC_P0_HIZ_QUAD_PER_TILE_H7               = 0x000000ae,
SC_P0_HIZ_QUAD_PER_TILE_H8               = 0x000000af,
SC_P0_HIZ_QUAD_PER_TILE_H9               = 0x000000b0,
SC_P0_HIZ_QUAD_PER_TILE_H10              = 0x000000b1,
SC_P0_HIZ_QUAD_PER_TILE_H11              = 0x000000b2,
SC_P0_HIZ_QUAD_PER_TILE_H12              = 0x000000b3,
SC_P0_HIZ_QUAD_PER_TILE_H13              = 0x000000b4,
SC_P0_HIZ_QUAD_PER_TILE_H14              = 0x000000b5,
SC_P0_HIZ_QUAD_PER_TILE_H15              = 0x000000b6,
SC_P0_HIZ_QUAD_PER_TILE_H16              = 0x000000b7,
SC_P1_HIZ_QUAD_PER_TILE_H0               = 0x000000b8,
SC_P1_HIZ_QUAD_PER_TILE_H1               = 0x000000b9,
SC_P1_HIZ_QUAD_PER_TILE_H2               = 0x000000ba,
SC_P1_HIZ_QUAD_PER_TILE_H3               = 0x000000bb,
SC_P1_HIZ_QUAD_PER_TILE_H4               = 0x000000bc,
SC_P1_HIZ_QUAD_PER_TILE_H5               = 0x000000bd,
SC_P1_HIZ_QUAD_PER_TILE_H6               = 0x000000be,
SC_P1_HIZ_QUAD_PER_TILE_H7               = 0x000000bf,
SC_P1_HIZ_QUAD_PER_TILE_H8               = 0x000000c0,
SC_P1_HIZ_QUAD_PER_TILE_H9               = 0x000000c1,
SC_P1_HIZ_QUAD_PER_TILE_H10              = 0x000000c2,
SC_P1_HIZ_QUAD_PER_TILE_H11              = 0x000000c3,
SC_P1_HIZ_QUAD_PER_TILE_H12              = 0x000000c4,
SC_P1_HIZ_QUAD_PER_TILE_H13              = 0x000000c5,
SC_P1_HIZ_QUAD_PER_TILE_H14              = 0x000000c6,
SC_P1_HIZ_QUAD_PER_TILE_H15              = 0x000000c7,
SC_P1_HIZ_QUAD_PER_TILE_H16              = 0x000000c8,
SC_P2_HIZ_QUAD_PER_TILE_H0               = 0x000000c9,
SC_P2_HIZ_QUAD_PER_TILE_H1               = 0x000000ca,
SC_P2_HIZ_QUAD_PER_TILE_H2               = 0x000000cb,
SC_P2_HIZ_QUAD_PER_TILE_H3               = 0x000000cc,
SC_P2_HIZ_QUAD_PER_TILE_H4               = 0x000000cd,
SC_P2_HIZ_QUAD_PER_TILE_H5               = 0x000000ce,
SC_P2_HIZ_QUAD_PER_TILE_H6               = 0x000000cf,
SC_P2_HIZ_QUAD_PER_TILE_H7               = 0x000000d0,
SC_P2_HIZ_QUAD_PER_TILE_H8               = 0x000000d1,
SC_P2_HIZ_QUAD_PER_TILE_H9               = 0x000000d2,
SC_P2_HIZ_QUAD_PER_TILE_H10              = 0x000000d3,
SC_P2_HIZ_QUAD_PER_TILE_H11              = 0x000000d4,
SC_P2_HIZ_QUAD_PER_TILE_H12              = 0x000000d5,
SC_P2_HIZ_QUAD_PER_TILE_H13              = 0x000000d6,
SC_P2_HIZ_QUAD_PER_TILE_H14              = 0x000000d7,
SC_P2_HIZ_QUAD_PER_TILE_H15              = 0x000000d8,
SC_P2_HIZ_QUAD_PER_TILE_H16              = 0x000000d9,
SC_P3_HIZ_QUAD_PER_TILE_H0               = 0x000000da,
SC_P3_HIZ_QUAD_PER_TILE_H1               = 0x000000db,
SC_P3_HIZ_QUAD_PER_TILE_H2               = 0x000000dc,
SC_P3_HIZ_QUAD_PER_TILE_H3               = 0x000000dd,
SC_P3_HIZ_QUAD_PER_TILE_H4               = 0x000000de,
SC_P3_HIZ_QUAD_PER_TILE_H5               = 0x000000df,
SC_P3_HIZ_QUAD_PER_TILE_H6               = 0x000000e0,
SC_P3_HIZ_QUAD_PER_TILE_H7               = 0x000000e1,
SC_P3_HIZ_QUAD_PER_TILE_H8               = 0x000000e2,
SC_P3_HIZ_QUAD_PER_TILE_H9               = 0x000000e3,
SC_P3_HIZ_QUAD_PER_TILE_H10              = 0x000000e4,
SC_P3_HIZ_QUAD_PER_TILE_H11              = 0x000000e5,
SC_P3_HIZ_QUAD_PER_TILE_H12              = 0x000000e6,
SC_P3_HIZ_QUAD_PER_TILE_H13              = 0x000000e7,
SC_P3_HIZ_QUAD_PER_TILE_H14              = 0x000000e8,
SC_P3_HIZ_QUAD_PER_TILE_H15              = 0x000000e9,
SC_P3_HIZ_QUAD_PER_TILE_H16              = 0x000000ea,
SC_P0_HIZ_QUAD_COUNT                     = 0x000000eb,
SC_P1_HIZ_QUAD_COUNT                     = 0x000000ec,
SC_P2_HIZ_QUAD_COUNT                     = 0x000000ed,
SC_P3_HIZ_QUAD_COUNT                     = 0x000000ee,
SC_P0_DETAIL_QUAD_COUNT                  = 0x000000ef,
SC_P1_DETAIL_QUAD_COUNT                  = 0x000000f0,
SC_P2_DETAIL_QUAD_COUNT                  = 0x000000f1,
SC_P3_DETAIL_QUAD_COUNT                  = 0x000000f2,
SC_P0_DETAIL_QUAD_WITH_1_PIX             = 0x000000f3,
SC_P0_DETAIL_QUAD_WITH_2_PIX             = 0x000000f4,
SC_P0_DETAIL_QUAD_WITH_3_PIX             = 0x000000f5,
SC_P0_DETAIL_QUAD_WITH_4_PIX             = 0x000000f6,
SC_P1_DETAIL_QUAD_WITH_1_PIX             = 0x000000f7,
SC_P1_DETAIL_QUAD_WITH_2_PIX             = 0x000000f8,
SC_P1_DETAIL_QUAD_WITH_3_PIX             = 0x000000f9,
SC_P1_DETAIL_QUAD_WITH_4_PIX             = 0x000000fa,
SC_P2_DETAIL_QUAD_WITH_1_PIX             = 0x000000fb,
SC_P2_DETAIL_QUAD_WITH_2_PIX             = 0x000000fc,
SC_P2_DETAIL_QUAD_WITH_3_PIX             = 0x000000fd,
SC_P2_DETAIL_QUAD_WITH_4_PIX             = 0x000000fe,
SC_P3_DETAIL_QUAD_WITH_1_PIX             = 0x000000ff,
SC_P3_DETAIL_QUAD_WITH_2_PIX             = 0x00000100,
SC_P3_DETAIL_QUAD_WITH_3_PIX             = 0x00000101,
SC_P3_DETAIL_QUAD_WITH_4_PIX             = 0x00000102,
SC_EARLYZ_QUAD_COUNT                     = 0x00000103,
SC_EARLYZ_QUAD_WITH_1_PIX                = 0x00000104,
SC_EARLYZ_QUAD_WITH_2_PIX                = 0x00000105,
SC_EARLYZ_QUAD_WITH_3_PIX                = 0x00000106,
SC_EARLYZ_QUAD_WITH_4_PIX                = 0x00000107,
SC_PKR_QUAD_PER_ROW_H1                   = 0x00000108,
SC_PKR_QUAD_PER_ROW_H2                   = 0x00000109,
SC_PKR_4X2_QUAD_SPLIT                    = 0x0000010a,
SC_PKR_4X2_FILL_QUAD                     = 0x0000010b,
SC_PKR_END_OF_VECTOR                     = 0x0000010c,
SC_PKR_CONTROL_XFER                      = 0x0000010d,
SC_PKR_DBHANG_FORCE_EOV                  = 0x0000010e,
SC_REG_SCLK_BUSY                         = 0x0000010f,
SC_GRP0_DYN_SCLK_BUSY                    = 0x00000110,
SC_GRP1_DYN_SCLK_BUSY                    = 0x00000111,
SC_GRP2_DYN_SCLK_BUSY                    = 0x00000112,
SC_GRP3_DYN_SCLK_BUSY                    = 0x00000113,
SC_GRP4_DYN_SCLK_BUSY                    = 0x00000114,
SC_PA0_SC_DATA_FIFO_RD                   = 0x00000115,
SC_PA0_SC_DATA_FIFO_WE                   = 0x00000116,
SC_PA1_SC_DATA_FIFO_RD                   = 0x00000117,
SC_PA1_SC_DATA_FIFO_WE                   = 0x00000118,
SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES   = 0x00000119,
SC_PS_ARB_XFC_ONLY_PRIM_CYCLES           = 0x0000011a,
SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM      = 0x0000011b,
SC_PS_ARB_STALLED_FROM_BELOW             = 0x0000011c,
SC_PS_ARB_STARVED_FROM_ABOVE             = 0x0000011d,
SC_PS_ARB_SC_BUSY                        = 0x0000011e,
SC_PS_ARB_PA_SC_BUSY                     = 0x0000011f,
SC_PA2_SC_DATA_FIFO_RD                   = 0x00000120,
SC_PA2_SC_DATA_FIFO_WE                   = 0x00000121,
SC_PA3_SC_DATA_FIFO_RD                   = 0x00000122,
SC_PA3_SC_DATA_FIFO_WE                   = 0x00000123,
SC_PA_SC_DEALLOC_0_0_WE                  = 0x00000124,
SC_PA_SC_DEALLOC_0_1_WE                  = 0x00000125,
SC_PA_SC_DEALLOC_1_0_WE                  = 0x00000126,
SC_PA_SC_DEALLOC_1_1_WE                  = 0x00000127,
SC_PA_SC_DEALLOC_2_0_WE                  = 0x00000128,
SC_PA_SC_DEALLOC_2_1_WE                  = 0x00000129,
SC_PA_SC_DEALLOC_3_0_WE                  = 0x0000012a,
SC_PA_SC_DEALLOC_3_1_WE                  = 0x0000012b,
SC_PA0_SC_EOP_WE                         = 0x0000012c,
SC_PA0_SC_EOPG_WE                        = 0x0000012d,
SC_PA0_SC_EVENT_WE                       = 0x0000012e,
SC_PA1_SC_EOP_WE                         = 0x0000012f,
SC_PA1_SC_EOPG_WE                        = 0x00000130,
SC_PA1_SC_EVENT_WE                       = 0x00000131,
SC_PA2_SC_EOP_WE                         = 0x00000132,
SC_PA2_SC_EOPG_WE                        = 0x00000133,
SC_PA2_SC_EVENT_WE                       = 0x00000134,
SC_PA3_SC_EOP_WE                         = 0x00000135,
SC_PA3_SC_EOPG_WE                        = 0x00000136,
SC_PA3_SC_EVENT_WE                       = 0x00000137,
SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138,
SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH          = 0x00000139,
SC_PS_ARB_NULL_PRIM_BUBBLE_POP           = 0x0000013a,
SC_PS_ARB_EOP_POP_SYNC_POP               = 0x0000013b,
SC_PS_ARB_EVENT_SYNC_POP                 = 0x0000013c,
SC_SC_PS_ENG_MULTICYCLE_BUBBLE           = 0x0000013d,
SC_PA0_SC_FPOV_WE                        = 0x0000013e,
SC_PA1_SC_FPOV_WE                        = 0x0000013f,
SC_PA2_SC_FPOV_WE                        = 0x00000140,
SC_PA3_SC_FPOV_WE                        = 0x00000141,
SC_PA0_SC_LPOV_WE                        = 0x00000142,
SC_PA1_SC_LPOV_WE                        = 0x00000143,
SC_PA2_SC_LPOV_WE                        = 0x00000144,
SC_PA3_SC_LPOV_WE                        = 0x00000145,
SC_SC_SPI_DEALLOC_0_0                    = 0x00000146,
SC_SC_SPI_DEALLOC_0_1                    = 0x00000147,
SC_SC_SPI_DEALLOC_0_2                    = 0x00000148,
SC_SC_SPI_DEALLOC_1_0                    = 0x00000149,
SC_SC_SPI_DEALLOC_1_1                    = 0x0000014a,
SC_SC_SPI_DEALLOC_1_2                    = 0x0000014b,
SC_SC_SPI_DEALLOC_2_0                    = 0x0000014c,
SC_SC_SPI_DEALLOC_2_1                    = 0x0000014d,
SC_SC_SPI_DEALLOC_2_2                    = 0x0000014e,
SC_SC_SPI_DEALLOC_3_0                    = 0x0000014f,
SC_SC_SPI_DEALLOC_3_1                    = 0x00000150,
SC_SC_SPI_DEALLOC_3_2                    = 0x00000151,
SC_SC_SPI_FPOV_0                         = 0x00000152,
SC_SC_SPI_FPOV_1                         = 0x00000153,
SC_SC_SPI_FPOV_2                         = 0x00000154,
SC_SC_SPI_FPOV_3                         = 0x00000155,
SC_SC_SPI_EVENT                          = 0x00000156,
SC_PS_TS_EVENT_FIFO_PUSH                 = 0x00000157,
SC_PS_TS_EVENT_FIFO_POP                  = 0x00000158,
SC_PS_CTX_DONE_FIFO_PUSH                 = 0x00000159,
SC_PS_CTX_DONE_FIFO_POP                  = 0x0000015a,
SC_MULTICYCLE_BUBBLE_FREEZE              = 0x0000015b,
SC_EOP_SYNC_WINDOW                       = 0x0000015c,
SC_PA0_SC_NULL_WE                        = 0x0000015d,
SC_PA0_SC_NULL_DEALLOC_WE                = 0x0000015e,
SC_PA0_SC_DATA_FIFO_EOPG_RD              = 0x0000015f,
SC_PA0_SC_DATA_FIFO_EOP_RD               = 0x00000160,
SC_PA0_SC_DEALLOC_0_RD                   = 0x00000161,
SC_PA0_SC_DEALLOC_1_RD                   = 0x00000162,
SC_PA1_SC_DATA_FIFO_EOPG_RD              = 0x00000163,
SC_PA1_SC_DATA_FIFO_EOP_RD               = 0x00000164,
SC_PA1_SC_DEALLOC_0_RD                   = 0x00000165,
SC_PA1_SC_DEALLOC_1_RD                   = 0x00000166,
SC_PA1_SC_NULL_WE                        = 0x00000167,
SC_PA1_SC_NULL_DEALLOC_WE                = 0x00000168,
SC_PA2_SC_DATA_FIFO_EOPG_RD              = 0x00000169,
SC_PA2_SC_DATA_FIFO_EOP_RD               = 0x0000016a,
SC_PA2_SC_DEALLOC_0_RD                   = 0x0000016b,
SC_PA2_SC_DEALLOC_1_RD                   = 0x0000016c,
SC_PA2_SC_NULL_WE                        = 0x0000016d,
SC_PA2_SC_NULL_DEALLOC_WE                = 0x0000016e,
SC_PA3_SC_DATA_FIFO_EOPG_RD              = 0x0000016f,
SC_PA3_SC_DATA_FIFO_EOP_RD               = 0x00000170,
SC_PA3_SC_DEALLOC_0_RD                   = 0x00000171,
SC_PA3_SC_DEALLOC_1_RD                   = 0x00000172,
SC_PA3_SC_NULL_WE                        = 0x00000173,
SC_PA3_SC_NULL_DEALLOC_WE                = 0x00000174,
SC_PS_PA0_SC_FIFO_EMPTY                  = 0x00000175,
SC_PS_PA0_SC_FIFO_FULL                   = 0x00000176,
SC_PS_PA1_SC_FIFO_EMPTY                  = 0x00000178,
SC_PS_PA1_SC_FIFO_FULL                   = 0x00000179,
SC_PS_PA2_SC_FIFO_EMPTY                  = 0x0000017b,
SC_PS_PA2_SC_FIFO_FULL                   = 0x0000017c,
SC_PS_PA3_SC_FIFO_EMPTY                  = 0x0000017e,
SC_PS_PA3_SC_FIFO_FULL                   = 0x0000017f,
SC_BUSY_PROCESSING_MULTICYCLE_PRIM       = 0x00000181,
SC_BUSY_CNT_NOT_ZERO                     = 0x00000182,
SC_BM_BUSY                               = 0x00000183,
SC_BACKEND_BUSY                          = 0x00000184,
SC_SCF_SCB_INTERFACE_BUSY                = 0x00000185,
SC_SCB_BUSY                              = 0x00000186,
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187,
SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188,
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX      = 0x000001e9,
SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea,
} SC_PERFCNT_SEL;

typedef enum SDMA_PERF_SEL {
SDMA_PERF_SEL_CYCLE                      = 0x00000000,
SDMA_PERF_SEL_IDLE                       = 0x00000001,
SDMA_PERF_SEL_REG_IDLE                   = 0x00000002,
SDMA_PERF_SEL_RB_EMPTY                   = 0x00000003,
SDMA_PERF_SEL_RB_FULL                    = 0x00000004,
SDMA_PERF_SEL_RB_WPTR_WRAP               = 0x00000005,
SDMA_PERF_SEL_RB_RPTR_WRAP               = 0x00000006,
SDMA_PERF_SEL_RB_WPTR_POLL_READ          = 0x00000007,
SDMA_PERF_SEL_RB_RPTR_WB                 = 0x00000008,
SDMA_PERF_SEL_RB_CMD_IDLE                = 0x00000009,
SDMA_PERF_SEL_RB_CMD_FULL                = 0x0000000a,
SDMA_PERF_SEL_IB_CMD_IDLE                = 0x0000000b,
SDMA_PERF_SEL_IB_CMD_FULL                = 0x0000000c,
SDMA_PERF_SEL_EX_IDLE                    = 0x0000000d,
SDMA_PERF_SEL_SRBM_REG_SEND              = 0x0000000e,
SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE  = 0x0000000f,
SDMA_PERF_SEL_MC_WR_IDLE                 = 0x00000010,
SDMA_PERF_SEL_MC_WR_COUNT                = 0x00000011,
SDMA_PERF_SEL_MC_RD_IDLE                 = 0x00000012,
SDMA_PERF_SEL_MC_RD_COUNT                = 0x00000013,
SDMA_PERF_SEL_MC_RD_RET_STALL            = 0x00000014,
SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE         = 0x00000015,
SDMA_PERF_SEL_SEM_IDLE                   = 0x00000018,
SDMA_PERF_SEL_SEM_REQ_STALL              = 0x00000019,
SDMA_PERF_SEL_SEM_REQ_COUNT              = 0x0000001a,
SDMA_PERF_SEL_SEM_RESP_INCOMPLETE        = 0x0000001b,
SDMA_PERF_SEL_SEM_RESP_FAIL              = 0x0000001c,
SDMA_PERF_SEL_SEM_RESP_PASS              = 0x0000001d,
SDMA_PERF_SEL_INT_IDLE                   = 0x0000001e,
SDMA_PERF_SEL_INT_REQ_STALL              = 0x0000001f,
SDMA_PERF_SEL_INT_REQ_COUNT              = 0x00000020,
SDMA_PERF_SEL_INT_RESP_ACCEPTED          = 0x00000021,
SDMA_PERF_SEL_INT_RESP_RETRY             = 0x00000022,
SDMA_PERF_SEL_NUM_PACKET                 = 0x00000023,
SDMA_PERF_SEL_CE_WREQ_IDLE               = 0x00000025,
SDMA_PERF_SEL_CE_WR_IDLE                 = 0x00000026,
SDMA_PERF_SEL_CE_SPLIT_IDLE              = 0x00000027,
SDMA_PERF_SEL_CE_RREQ_IDLE               = 0x00000028,
SDMA_PERF_SEL_CE_OUT_IDLE                = 0x00000029,
SDMA_PERF_SEL_CE_IN_IDLE                 = 0x0000002a,
SDMA_PERF_SEL_CE_DST_IDLE                = 0x0000002b,
SDMA_PERF_SEL_CE_AFIFO_FULL              = 0x0000002e,
SDMA_PERF_SEL_CE_INFO_FULL               = 0x00000031,
SDMA_PERF_SEL_CE_INFO1_FULL              = 0x00000032,
SDMA_PERF_SEL_CE_RD_STALL                = 0x00000033,
SDMA_PERF_SEL_CE_WR_STALL                = 0x00000034,
SDMA_PERF_SEL_GFX_SELECT                 = 0x00000035,
SDMA_PERF_SEL_RLC0_SELECT                = 0x00000036,
SDMA_PERF_SEL_RLC1_SELECT                = 0x00000037,
SDMA_PERF_SEL_CTX_CHANGE                 = 0x00000039,
SDMA_PERF_SEL_CTX_CHANGE_EXPIRED         = 0x0000003a,
SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION       = 0x0000003b,
SDMA_PERF_SEL_DOORBELL                   = 0x0000003c,
SDMA_PERF_SEL_RD_BA_RTR                  = 0x0000003d,
SDMA_PERF_SEL_WR_BA_RTR                  = 0x0000003e,
SDMA_PERF_SEL_F32_L1_WR_VLD              = 0x0000003f,
SDMA_PERF_SEL_CE_L1_WR_VLD               = 0x00000040,
SDMA_PERF_SEL_CE_L1_STALL__GFX09         = 0x00000041,
SDMA_PERF_SEL_SDMA_INVACK_NFLUSH__GFX09  = 0x00000042,
SDMA_PERF_SEL_SDMA_INVACK_FLUSH__GFX09   = 0x00000043,
SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH__GFX09 = 0x00000044,
SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH__GFX09  = 0x00000045,
SDMA_PERF_SEL_ATCL2_RET_XNACK__GFX09     = 0x00000046,
SDMA_PERF_SEL_ATCL2_RET_ACK__GFX09       = 0x00000047,
SDMA_PERF_SEL_ATCL2_FREE__GFX09          = 0x00000048,
SDMA_PERF_SEL_SDMA_ATCL2_SEND__GFX09     = 0x00000049,
SDMA_PERF_SEL_DMA_L1_WR_SEND__GFX09      = 0x0000004a,
SDMA_PERF_SEL_DMA_L1_RD_SEND__GFX09      = 0x0000004b,
SDMA_PERF_SEL_DMA_MC_WR_SEND__GFX09      = 0x0000004c,
SDMA_PERF_SEL_DMA_MC_RD_SEND__GFX09      = 0x0000004d,
SDMA_PERF_SEL_L1_WR_FIFO_IDLE__GFX09     = 0x0000004e,
SDMA_PERF_SEL_L1_RD_FIFO_IDLE__GFX09     = 0x0000004f,
SDMA_PERF_SEL_L1_WRL2_IDLE__GFX09        = 0x00000050,
SDMA_PERF_SEL_L1_RDL2_IDLE__GFX09        = 0x00000051,
SDMA_PERF_SEL_L1_WRMC_IDLE__GFX09        = 0x00000052,
SDMA_PERF_SEL_L1_RDMC_IDLE__GFX09        = 0x00000053,
SDMA_PERF_SEL_L1_WR_INV_IDLE__GFX09      = 0x00000054,
SDMA_PERF_SEL_L1_RD_INV_IDLE__GFX09      = 0x00000055,
SDMA_PERF_SEL_L1_WR_INV_EN__GFX09        = 0x00000056,
SDMA_PERF_SEL_L1_RD_INV_EN__GFX09        = 0x00000057,
SDMA_PERF_SEL_L1_WR_WAIT_INVADR__GFX09   = 0x00000058,
SDMA_PERF_SEL_L1_RD_WAIT_INVADR__GFX09   = 0x00000059,
SDMA_PERF_SEL_IS_INVREQ_ADDR_WR__GFX09   = 0x0000005a,
SDMA_PERF_SEL_IS_INVREQ_ADDR_RD__GFX09   = 0x0000005b,
SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT__GFX09 = 0x0000005c,
SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT__GFX09 = 0x0000005d,
SDMA_PERF_SEL_L1_INV_MIDDLE__GFX09       = 0x0000005e,
SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER__GFX09 = 0x000000ff,
} SDMA_PERF_SEL;

typedef enum SEM_PERF_SEL {
SEM_PERF_SEL_CYCLE                       = 0x00000000,
SEM_PERF_SEL_IDLE                        = 0x00000001,
SEM_PERF_SEL_SDMA0_REQ_SIGNAL            = 0x00000002,
SEM_PERF_SEL_SDMA1_REQ_SIGNAL            = 0x00000003,
SEM_PERF_SEL_UVD_REQ_SIGNAL              = 0x00000004,
SEM_PERF_SEL_VCE0_REQ_SIGNAL             = 0x00000005,
SEM_PERF_SEL_ACP_REQ_SIGNAL              = 0x00000006,
SEM_PERF_SEL_ISP_REQ_SIGNAL              = 0x00000007,
SEM_PERF_SEL_VCE1_REQ_SIGNAL             = 0x00000008,
SEM_PERF_SEL_VP8_REQ_SIGNAL              = 0x00000009,
SEM_PERF_SEL_CPG_E0_REQ_SIGNAL           = 0x0000000a,
SEM_PERF_SEL_CPG_E1_REQ_SIGNAL           = 0x0000000b,
SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL     = 0x0000000c,
SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL     = 0x0000000d,
SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL     = 0x0000000e,
SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL     = 0x0000000f,
SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL     = 0x00000010,
SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL     = 0x00000011,
SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL     = 0x00000012,
SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL     = 0x00000013,
SEM_PERF_SEL_SDMA0_REQ_WAIT              = 0x00000014,
SEM_PERF_SEL_SDMA1_REQ_WAIT              = 0x00000015,
SEM_PERF_SEL_UVD_REQ_WAIT                = 0x00000016,
SEM_PERF_SEL_VCE0_REQ_WAIT               = 0x00000017,
SEM_PERF_SEL_ACP_REQ_WAIT                = 0x00000018,
SEM_PERF_SEL_ISP_REQ_WAIT                = 0x00000019,
SEM_PERF_SEL_VCE1_REQ_WAIT               = 0x0000001a,
SEM_PERF_SEL_VP8_REQ_WAIT                = 0x0000001b,
SEM_PERF_SEL_CPG_E0_REQ_WAIT             = 0x0000001c,
SEM_PERF_SEL_CPG_E1_REQ_WAIT             = 0x0000001d,
SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT       = 0x0000001e,
SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT       = 0x0000001f,
SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT       = 0x00000020,
SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT       = 0x00000021,
SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT       = 0x00000022,
SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT       = 0x00000023,
SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT       = 0x00000024,
SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT       = 0x00000025,
SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT       = 0x00000026,
SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT       = 0x00000027,
SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT       = 0x00000028,
SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT       = 0x00000029,
SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT       = 0x0000002a,
SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT       = 0x0000002b,
SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT       = 0x0000002c,
SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT       = 0x0000002d,
SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT       = 0x0000002e,
SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT       = 0x0000002f,
SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT      = 0x00000030,
SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT      = 0x00000031,
SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT      = 0x00000032,
SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT      = 0x00000033,
SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT      = 0x00000034,
SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT      = 0x00000035,
SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT      = 0x00000036,
SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT      = 0x00000037,
SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT      = 0x00000038,
SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT      = 0x00000039,
SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT      = 0x0000003a,
SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT      = 0x0000003b,
SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT      = 0x0000003c,
SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT      = 0x0000003d,
SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT      = 0x0000003e,
SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT      = 0x0000003f,
SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT      = 0x00000040,
SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT      = 0x00000041,
SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT      = 0x00000042,
SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT      = 0x00000043,
SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT      = 0x00000044,
SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT      = 0x00000045,
SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT       = 0x00000046,
SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT       = 0x00000047,
SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT       = 0x00000048,
SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT       = 0x00000049,
SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT       = 0x0000004a,
SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT       = 0x0000004b,
SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT       = 0x0000004c,
SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT       = 0x0000004d,
SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT       = 0x0000004e,
SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT       = 0x0000004f,
SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT      = 0x00000050,
SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT      = 0x00000051,
SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT      = 0x00000052,
SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT      = 0x00000053,
SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT      = 0x00000054,
SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT      = 0x00000055,
SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT      = 0x00000056,
SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT      = 0x00000057,
SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT      = 0x00000058,
SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT      = 0x00000059,
SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT      = 0x0000005a,
SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT      = 0x0000005b,
SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT      = 0x0000005c,
SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT      = 0x0000005d,
SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT      = 0x0000005e,
SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT      = 0x0000005f,
SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT      = 0x00000060,
SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT      = 0x00000061,
SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT      = 0x00000062,
SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT      = 0x00000063,
SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT      = 0x00000064,
SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT      = 0x00000065,
SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT      = 0x00000066,
SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT      = 0x00000067,
SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT      = 0x00000068,
SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT      = 0x00000069,
SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT      = 0x0000006a,
SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT      = 0x0000006b,
SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT      = 0x0000006c,
SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT      = 0x0000006d,
SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT      = 0x0000006e,
SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT      = 0x0000006f,
SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT     = 0x00000070,
SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT     = 0x00000071,
SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT     = 0x00000072,
SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT     = 0x00000073,
SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT     = 0x00000074,
SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT     = 0x00000075,
SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT     = 0x00000076,
SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT     = 0x00000077,
SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT     = 0x00000078,
SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT     = 0x00000079,
SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT     = 0x0000007a,
SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT     = 0x0000007b,
SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT     = 0x0000007c,
SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT     = 0x0000007d,
SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT     = 0x0000007e,
SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT     = 0x0000007f,
SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT     = 0x00000080,
SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT     = 0x00000081,
SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT     = 0x00000082,
SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT     = 0x00000083,
SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT     = 0x00000084,
SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT     = 0x00000085,
SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT      = 0x00000086,
SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT      = 0x00000087,
SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT      = 0x00000088,
SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT      = 0x00000089,
SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT      = 0x0000008a,
SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT      = 0x0000008b,
SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT      = 0x0000008c,
SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT      = 0x0000008d,
SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT      = 0x0000008e,
SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT      = 0x0000008f,
SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT     = 0x00000090,
SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT     = 0x00000091,
SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT     = 0x00000092,
SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT     = 0x00000093,
SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT     = 0x00000094,
SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT     = 0x00000095,
SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT     = 0x00000096,
SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT     = 0x00000097,
SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT     = 0x00000098,
SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT     = 0x00000099,
SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT     = 0x0000009a,
SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT     = 0x0000009b,
SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT     = 0x0000009c,
SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT     = 0x0000009d,
SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT     = 0x0000009e,
SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT     = 0x0000009f,
SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT     = 0x000000a0,
SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT     = 0x000000a1,
SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT     = 0x000000a2,
SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT     = 0x000000a3,
SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT     = 0x000000a4,
SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT     = 0x000000a5,
SEM_PERF_SEL_MC_RD_REQ                   = 0x000000a6,
SEM_PERF_SEL_MC_RD_RET                   = 0x000000a7,
SEM_PERF_SEL_MC_WR_REQ                   = 0x000000a8,
SEM_PERF_SEL_MC_WR_RET                   = 0x000000a9,
SEM_PERF_SEL_ATC_REQ                     = 0x000000aa,
SEM_PERF_SEL_ATC_RET                     = 0x000000ab,
SEM_PERF_SEL_ATC_XNACK                   = 0x000000ac,
SEM_PERF_SEL_ATC_INVALIDATION            = 0x000000ad,
} SEM_PERF_SEL;

typedef enum SH_MEM_ADDRESS_MODE {
} SH_MEM_ADDRESS_MODE;

typedef enum SH_MEM_ALIGNMENT_MODE {
SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
SH_MEM_ALIGNMENT_MODE_DWORD_STRICT       = 0x00000001,
SH_MEM_ALIGNMENT_MODE_STRICT             = 0x00000002,
SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000003,
} SH_MEM_ALIGNMENT_MODE;

typedef enum SPI_FOG_MODE {
SPI_FOG_NONE                             = 0x00000000,
SPI_FOG_EXP                              = 0x00000001,
SPI_FOG_EXP2                             = 0x00000002,
SPI_FOG_LINEAR                           = 0x00000003,
} SPI_FOG_MODE;

typedef enum SPI_PERFCNT_SEL {
SPI_PERF_VS_WINDOW_VALID                 = 0x00000000,
SPI_PERF_VS_BUSY                         = 0x00000001,
SPI_PERF_VS_FIRST_WAVE                   = 0x00000002,
SPI_PERF_VS_LAST_WAVE                    = 0x00000003,
SPI_PERF_VS_LSHS_DEALLOC                 = 0x00000004,
SPI_PERF_VS_PC_STALL__GFX09              = 0x00000005,
SPI_PERF_VS_POS0_STALL__GFX09            = 0x00000006,
SPI_PERF_VS_POS1_STALL__GFX09            = 0x00000007,
SPI_PERF_VS_CRAWLER_STALL__GFX09         = 0x00000008,
SPI_PERF_VS_EVENT_WAVE__GFX09            = 0x00000009,
SPI_PERF_VS_WAVE__GFX09                  = 0x0000000a,
SPI_PERF_VS_PERS_UPD_FULL0__GFX09        = 0x0000000b,
SPI_PERF_VS_PERS_UPD_FULL1__GFX09        = 0x0000000c,
SPI_PERF_VS_LATE_ALLOC_FULL__GFX09       = 0x0000000d,
SPI_PERF_VS_FIRST_SUBGRP__GFX09          = 0x0000000e,
SPI_PERF_VS_LAST_SUBGRP__GFX09           = 0x0000000f,
SPI_PERF_VS_ALLOC_CNT__GFX09             = 0x00000010,
SPI_PERF_VS_LATE_ALLOC_ACCUM__GFX09      = 0x00000012,
SPI_PERF_GS_WINDOW_VALID__GFX09          = 0x00000013,
SPI_PERF_GS_BUSY__GFX09                  = 0x00000014,
SPI_PERF_GS_CRAWLER_STALL__GFX09         = 0x00000015,
SPI_PERF_GS_EVENT_WAVE__GFX09            = 0x00000016,
SPI_PERF_GS_WAVE__GFX09                  = 0x00000017,
SPI_PERF_GS_PERS_UPD_FULL0__GFX09        = 0x00000018,
SPI_PERF_GS_PERS_UPD_FULL1__GFX09        = 0x00000019,
SPI_PERF_GS_FIRST_SUBGRP__GFX09          = 0x0000001a,
SPI_PERF_GS_LAST_SUBGRP__GFX09           = 0x0000001b,
SPI_PERF_GS_GRP_FIFO_FULL__GFX09         = 0x0000001e,
SPI_PERF_HS_WINDOW_VALID__GFX09          = 0x0000001f,
SPI_PERF_HS_BUSY__GFX09                  = 0x00000020,
SPI_PERF_HS_CRAWLER_STALL__GFX09         = 0x00000021,
SPI_PERF_HS_FIRST_WAVE__GFX09            = 0x00000022,
SPI_PERF_HS_LAST_WAVE__GFX09             = 0x00000023,
SPI_PERF_HS_EVENT_WAVE__GFX09            = 0x00000025,
SPI_PERF_HS_WAVE__GFX09                  = 0x00000026,
SPI_PERF_HS_PERS_UPD_FULL0__GFX09        = 0x00000027,
SPI_PERF_HS_PERS_UPD_FULL1__GFX09        = 0x00000028,
SPI_PERF_CSG_WINDOW_VALID__GFX09         = 0x00000029,
SPI_PERF_CSG_BUSY__GFX09                 = 0x0000002a,
SPI_PERF_CSG_NUM_THREADGROUPS__GFX09     = 0x0000002b,
SPI_PERF_CSG_CRAWLER_STALL__GFX09        = 0x0000002c,
SPI_PERF_CSG_EVENT_WAVE__GFX09           = 0x0000002d,
SPI_PERF_CSG_WAVE__GFX09                 = 0x0000002e,
SPI_PERF_CSN_WINDOW_VALID__GFX09         = 0x0000002f,
SPI_PERF_CSN_BUSY__GFX09                 = 0x00000030,
SPI_PERF_CSN_NUM_THREADGROUPS__GFX09     = 0x00000031,
SPI_PERF_CSN_CRAWLER_STALL__GFX09        = 0x00000032,
SPI_PERF_CSN_EVENT_WAVE__GFX09           = 0x00000033,
SPI_PERF_CSN_WAVE__GFX09                 = 0x00000034,
SPI_PERF_PS_PERS_UPD_FULL0__GFX09        = 0x00000046,
SPI_PERF_PS_PERS_UPD_FULL1__GFX09        = 0x00000047,
SPI_PERF_LDS0_PC_VALID__GFX09            = 0x0000004a,
SPI_PERF_LDS1_PC_VALID__GFX09            = 0x0000004b,
SPI_PERF_RA_PIPE_REQ_BIN2__GFX09         = 0x0000004c,
SPI_PERF_RA_TASK_REQ_BIN3__GFX09         = 0x0000004d,
SPI_PERF_RA_WR_CTL_FULL__GFX09           = 0x0000004e,
SPI_PERF_RA_REQ_NO_ALLOC__GFX09          = 0x0000004f,
SPI_PERF_RA_REQ_NO_ALLOC_PS__GFX09       = 0x00000050,
SPI_PERF_RA_REQ_NO_ALLOC_VS__GFX09       = 0x00000051,
SPI_PERF_RA_REQ_NO_ALLOC_GS__GFX09       = 0x00000052,
SPI_PERF_RA_REQ_NO_ALLOC_HS__GFX09       = 0x00000053,
SPI_PERF_RA_REQ_NO_ALLOC_CSG__GFX09      = 0x00000054,
SPI_PERF_RA_REQ_NO_ALLOC_CSN__GFX09      = 0x00000055,
SPI_PERF_RA_RES_STALL_PS__GFX09          = 0x00000056,
SPI_PERF_RA_RES_STALL_VS__GFX09          = 0x00000057,
SPI_PERF_RA_RES_STALL_GS__GFX09          = 0x00000058,
SPI_PERF_RA_RES_STALL_HS__GFX09          = 0x00000059,
SPI_PERF_RA_RES_STALL_CSG__GFX09         = 0x0000005a,
SPI_PERF_RA_RES_STALL_CSN__GFX09         = 0x0000005b,
SPI_PERF_RA_TMP_STALL_PS__GFX09          = 0x0000005c,
SPI_PERF_RA_TMP_STALL_VS__GFX09          = 0x0000005d,
SPI_PERF_RA_TMP_STALL_GS__GFX09          = 0x0000005e,
SPI_PERF_RA_TMP_STALL_HS__GFX09          = 0x0000005f,
SPI_PERF_RA_TMP_STALL_CSG__GFX09         = 0x00000060,
SPI_PERF_RA_TMP_STALL_CSN__GFX09         = 0x00000061,
SPI_PERF_RA_WAVE_SIMD_FULL_PS__GFX09     = 0x00000062,
SPI_PERF_RA_WAVE_SIMD_FULL_VS__GFX09     = 0x00000063,
SPI_PERF_RA_WAVE_SIMD_FULL_GS__GFX09     = 0x00000064,
SPI_PERF_RA_WAVE_SIMD_FULL_HS__GFX09     = 0x00000065,
SPI_PERF_RA_WAVE_SIMD_FULL_CSG__GFX09    = 0x00000066,
SPI_PERF_RA_WAVE_SIMD_FULL_CSN__GFX09    = 0x00000067,
SPI_PERF_RA_VGPR_SIMD_FULL_PS__GFX09     = 0x00000068,
SPI_PERF_RA_VGPR_SIMD_FULL_VS__GFX09     = 0x00000069,
SPI_PERF_RA_VGPR_SIMD_FULL_GS__GFX09     = 0x0000006a,
SPI_PERF_RA_VGPR_SIMD_FULL_HS__GFX09     = 0x0000006b,
SPI_PERF_RA_VGPR_SIMD_FULL_CSG__GFX09    = 0x0000006c,
SPI_PERF_RA_VGPR_SIMD_FULL_CSN__GFX09    = 0x0000006d,
SPI_PERF_RA_SGPR_SIMD_FULL_PS__GFX09     = 0x0000006e,
SPI_PERF_RA_SGPR_SIMD_FULL_VS__GFX09     = 0x0000006f,
SPI_PERF_RA_SGPR_SIMD_FULL_GS__GFX09     = 0x00000070,
SPI_PERF_RA_SGPR_SIMD_FULL_HS__GFX09     = 0x00000071,
SPI_PERF_RA_SGPR_SIMD_FULL_CSG__GFX09    = 0x00000072,
SPI_PERF_RA_SGPR_SIMD_FULL_CSN__GFX09    = 0x00000073,
SPI_PERF_RA_LDS_CU_FULL_PS__GFX09        = 0x00000074,
SPI_PERF_RA_LDS_CU_FULL_LS__GFX09        = 0x00000075,
SPI_PERF_RA_LDS_CU_FULL_ES__GFX09        = 0x00000076,
SPI_PERF_RA_LDS_CU_FULL_CSG__GFX09       = 0x00000077,
SPI_PERF_RA_LDS_CU_FULL_CSN__GFX09       = 0x00000078,
SPI_PERF_RA_BAR_CU_FULL_HS__GFX09        = 0x00000079,
SPI_PERF_RA_BAR_CU_FULL_CSG__GFX09       = 0x0000007a,
SPI_PERF_RA_BAR_CU_FULL_CSN__GFX09       = 0x0000007b,
SPI_PERF_RA_BULKY_CU_FULL_CSG__GFX09     = 0x0000007c,
SPI_PERF_RA_BULKY_CU_FULL_CSN__GFX09     = 0x0000007d,
SPI_PERF_RA_TGLIM_CU_FULL_CSG__GFX09     = 0x0000007e,
SPI_PERF_RA_TGLIM_CU_FULL_CSN__GFX09     = 0x0000007f,
SPI_PERF_RA_WVLIM_STALL_PS__GFX09        = 0x00000080,
SPI_PERF_RA_WVLIM_STALL_VS__GFX09        = 0x00000081,
SPI_PERF_RA_WVLIM_STALL_GS__GFX09        = 0x00000082,
SPI_PERF_RA_WVLIM_STALL_HS__GFX09        = 0x00000083,
SPI_PERF_RA_WVLIM_STALL_CSG__GFX09       = 0x00000084,
SPI_PERF_RA_WVLIM_STALL_CSN__GFX09       = 0x00000085,
SPI_PERF_RA_VS_LOCK__GFX09               = 0x00000086,
SPI_PERF_RA_GS_LOCK__GFX09               = 0x00000087,
SPI_PERF_RA_HS_LOCK__GFX09               = 0x00000088,
SPI_PERF_RA_CSG_LOCK__GFX09              = 0x00000089,
SPI_PERF_RA_CSN_LOCK__GFX09              = 0x0000008a,
SPI_PERF_RA_RSV_UPD__GFX09               = 0x0000008b,
SPI_PERF_EXP_ARB_COL_CNT__GFX09          = 0x0000008c,
SPI_PERF_EXP_ARB_PAR_CNT__GFX09          = 0x0000008d,
SPI_PERF_EXP_ARB_POS_CNT__GFX09          = 0x0000008e,
SPI_PERF_EXP_ARB_GDS_CNT__GFX09          = 0x0000008f,
SPI_PERF_CLKGATE_BUSY_STALL__GFX09       = 0x00000099,
SPI_PERF_CLKGATE_ACTIVE_STALL__GFX09     = 0x0000009a,
SPI_PERF_CLKGATE_ALL_CLOCKS_ON__GFX09    = 0x0000009b,
SPI_PERF_CLKGATE_CGTT_DYN_ON__GFX09      = 0x0000009c,
SPI_PERF_CLKGATE_CGTT_REG_ON__GFX09      = 0x0000009d,
SPI_PERF_PIX_ALLOC_PEND_CNT__GFX09       = 0x0000009e,
SPI_PERF_PIX_ALLOC_SCB_STALL__GFX09      = 0x0000009f,
SPI_PERF_PIX_ALLOC_DB0_STALL__GFX09      = 0x000000a0,
SPI_PERF_PIX_ALLOC_DB1_STALL__GFX09      = 0x000000a1,
SPI_PERF_PIX_ALLOC_DB2_STALL__GFX09      = 0x000000a2,
SPI_PERF_PIX_ALLOC_DB3_STALL__GFX09      = 0x000000a3,
SPI_PERF_PC_ALLOC_ACCUM__GFX09           = 0x000000a4,
SPI_PERF_VWC_CSC_WR__GFX09               = 0x000000c3,
} SPI_PERFCNT_SEL;

typedef enum SPI_PNT_SPRITE_OVERRIDE {
SPI_PNT_SPRITE_SEL_0                     = 0x00000000,
SPI_PNT_SPRITE_SEL_1                     = 0x00000001,
SPI_PNT_SPRITE_SEL_S                     = 0x00000002,
SPI_PNT_SPRITE_SEL_T                     = 0x00000003,
SPI_PNT_SPRITE_SEL_NONE                  = 0x00000004,
} SPI_PNT_SPRITE_OVERRIDE;

typedef enum SPI_SAMPLE_CNTL {
CENTROIDS_ONLY                           = 0x00000000,
CENTERS_ONLY                             = 0x00000001,
CENTROIDS_AND_CENTERS                    = 0x00000002,
UNDEF                                    = 0x00000003,
} SPI_SAMPLE_CNTL;

typedef enum SPI_SHADER_EX_FORMAT {
SPI_SHADER_ZERO                          = 0x00000000,
SPI_SHADER_32_R                          = 0x00000001,
SPI_SHADER_32_GR                         = 0x00000002,
SPI_SHADER_32_AR                         = 0x00000003,
SPI_SHADER_FP16_ABGR                     = 0x00000004,
SPI_SHADER_UNORM16_ABGR                  = 0x00000005,
SPI_SHADER_SNORM16_ABGR                  = 0x00000006,
SPI_SHADER_UINT16_ABGR                   = 0x00000007,
SPI_SHADER_SINT16_ABGR                   = 0x00000008,
SPI_SHADER_32_ABGR                       = 0x00000009,
} SPI_SHADER_EX_FORMAT;

typedef enum SPI_SHADER_FORMAT {
SPI_SHADER_NONE                          = 0x00000000,
SPI_SHADER_1COMP                         = 0x00000001,
SPI_SHADER_2COMP                         = 0x00000002,
SPI_SHADER_4COMPRESS                     = 0x00000003,
SPI_SHADER_4COMP                         = 0x00000004,
} SPI_SHADER_FORMAT;

typedef enum SPM_PERFMON_STATE {
STRM_PERFMON_STATE_DISABLE_AND_RESET     = 0x00000000,
STRM_PERFMON_STATE_START_COUNTING        = 0x00000001,
STRM_PERFMON_STATE_STOP_COUNTING         = 0x00000002,
STRM_PERFMON_STATE_RESERVED_3            = 0x00000003,
STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
} SPM_PERFMON_STATE;

typedef enum SQ_CAC_POWER_SEL {
SQ_CAC_POWER_VALU                        = 0x00000000,
SQ_CAC_POWER_VALU0                       = 0x00000001,
SQ_CAC_POWER_VALU1                       = 0x00000002,
SQ_CAC_POWER_VALU2                       = 0x00000003,
SQ_CAC_POWER_GPR_RD                      = 0x00000004,
SQ_CAC_POWER_GPR_WR                      = 0x00000005,
SQ_CAC_POWER_LDS_BUSY                    = 0x00000006,
SQ_CAC_POWER_ALU_BUSY                    = 0x00000007,
SQ_CAC_POWER_TEX_BUSY                    = 0x00000008,
} SQ_CAC_POWER_SEL;

typedef enum SQ_EDC_INFO_SOURCE {
SQ_EDC_INFO_SOURCE_INVALID               = 0x00000000,
SQ_EDC_INFO_SOURCE_INST                  = 0x00000001,
SQ_EDC_INFO_SOURCE_SGPR                  = 0x00000002,
SQ_EDC_INFO_SOURCE_VGPR                  = 0x00000003,
SQ_EDC_INFO_SOURCE_LDS                   = 0x00000004,
SQ_EDC_INFO_SOURCE_GDS                   = 0x00000005,
SQ_EDC_INFO_SOURCE_TA                    = 0x00000006,
} SQ_EDC_INFO_SOURCE;

typedef enum SQ_IBUF_ST {
SQ_IBUF_IB_IDLE                          = 0x00000000,
SQ_IBUF_IB_INI_WAIT_GNT                  = 0x00000001,
SQ_IBUF_IB_INI_WAIT_DRET                 = 0x00000002,
SQ_IBUF_IB_LE_4DW                        = 0x00000003,
SQ_IBUF_IB_WAIT_DRET                     = 0x00000004,
SQ_IBUF_IB_EMPTY_WAIT_DRET               = 0x00000005,
SQ_IBUF_IB_DRET                          = 0x00000006,
SQ_IBUF_IB_EMPTY_WAIT_GNT                = 0x00000007,
} SQ_IBUF_ST;

typedef enum SQ_IMG_FILTER_TYPE {
SQ_IMG_FILTER_MODE_BLEND                 = 0x00000000,
SQ_IMG_FILTER_MODE_MIN                   = 0x00000001,
SQ_IMG_FILTER_MODE_MAX                   = 0x00000002,
} SQ_IMG_FILTER_TYPE;

typedef enum SQ_IND_CMD_CMD {
SQ_IND_CMD_CMD_NULL                      = 0x00000000,
SQ_IND_CMD_CMD_SETHALT                   = 0x00000001,
SQ_IND_CMD_CMD_SAVECTX                   = 0x00000002,
SQ_IND_CMD_CMD_KILL                      = 0x00000003,
SQ_IND_CMD_CMD_DEBUG                     = 0x00000004,
SQ_IND_CMD_CMD_TRAP                      = 0x00000005,
SQ_IND_CMD_CMD_SET_SPI_PRIO              = 0x00000006,
} SQ_IND_CMD_CMD;

typedef enum SQ_IND_CMD_MODE {
SQ_IND_CMD_MODE_SINGLE                   = 0x00000000,
SQ_IND_CMD_MODE_BROADCAST                = 0x00000001,
SQ_IND_CMD_MODE_BROADCAST_QUEUE          = 0x00000002,
SQ_IND_CMD_MODE_BROADCAST_PIPE           = 0x00000003,
SQ_IND_CMD_MODE_BROADCAST_ME             = 0x00000004,
} SQ_IND_CMD_MODE;

typedef enum SQ_INST_STR_ST {
SQ_INST_STR_IB_WAVE_NORML                = 0x00000000,
SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV    = 0x00000001,
SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV     = 0x00000002,
SQ_INST_STR_IB_WAVE_INST_SKIP_AV         = 0x00000003,
SQ_INST_STR_IB_WAVE_SETVSKIP_ST0         = 0x00000004,
SQ_INST_STR_IB_WAVE_SETVSKIP_ST1         = 0x00000005,
SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT       = 0x00000006,
SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
} SQ_INST_STR_ST;

typedef enum SQ_INTERRUPT_WORD_ENCODING {
SQ_INTERRUPT_WORD_ENCODING_AUTO          = 0x00000000,
SQ_INTERRUPT_WORD_ENCODING_INST          = 0x00000001,
SQ_INTERRUPT_WORD_ENCODING_ERROR         = 0x00000002,
} SQ_INTERRUPT_WORD_ENCODING;

typedef enum SQ_LB_CTR_SEL_VALUES {
} SQ_LB_CTR_SEL_VALUES;

typedef enum SQ_PERF_SEL {
SQ_PERF_SEL_NONE                         = 0x00000000,
SQ_PERF_SEL_ACCUM_PREV                   = 0x00000001,
SQ_PERF_SEL_CYCLES                       = 0x00000002,
SQ_PERF_SEL_BUSY_CYCLES                  = 0x00000003,
SQ_PERF_SEL_WAVES                        = 0x00000004,
SQ_PERF_SEL_LEVEL_WAVES__GFX09           = 0x00000005,
SQ_PERF_SEL_WAVES_EQ_64__GFX09           = 0x00000006,
SQ_PERF_SEL_WAVES_LT_64__GFX09           = 0x00000007,
SQ_PERF_SEL_WAVES_LT_48__GFX09           = 0x00000008,
SQ_PERF_SEL_WAVES_LT_32__GFX09           = 0x00000009,
SQ_PERF_SEL_WAVES_LT_16__GFX09           = 0x0000000a,
SQ_PERF_SEL_WAVES_CU__GFX09              = 0x0000000b,
SQ_PERF_SEL_LEVEL_WAVES_CU__GFX09        = 0x0000000c,
SQ_PERF_SEL_BUSY_CU_CYCLES__GFX09        = 0x0000000d,
SQ_PERF_SEL_ITEMS__GFX09                 = 0x0000000e,
SQ_PERF_SEL_QUADS__GFX09                 = 0x0000000f,
SQ_PERF_SEL_EVENTS__GFX09                = 0x00000010,
SQ_PERF_SEL_SURF_SYNCS__GFX09            = 0x00000011,
SQ_PERF_SEL_TTRACE_REQS__GFX09           = 0x00000012,
SQ_PERF_SEL_TTRACE_INFLIGHT_REQS__GFX09  = 0x00000013,
SQ_PERF_SEL_TTRACE_STALL__GFX09          = 0x00000014,
SQ_PERF_SEL_MSG_CNTR__GFX09              = 0x00000015,
SQ_PERF_SEL_MSG_PERF__GFX09              = 0x00000016,
SQ_PERF_SEL_MSG_GSCNT__GFX09             = 0x00000017,
SQ_PERF_SEL_MSG_INTERRUPT__GFX09         = 0x00000018,
SQ_PERF_SEL_INSTS__GFX09                 = 0x00000019,
SQ_PERF_SEL_INSTS_VALU__GFX09            = 0x0000001a,
SQ_PERF_SEL_INSTS_VMEM_WR__GFX09         = 0x0000001b,
SQ_PERF_SEL_INSTS_VMEM_RD__GFX09         = 0x0000001c,
SQ_PERF_SEL_INSTS_VMEM__GFX09            = 0x0000001d,
SQ_PERF_SEL_INSTS_SALU__GFX09            = 0x0000001e,
SQ_PERF_SEL_INSTS_SMEM__GFX09            = 0x0000001f,
SQ_PERF_SEL_INSTS_FLAT__GFX09            = 0x00000020,
SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY__GFX09   = 0x00000021,
SQ_PERF_SEL_INSTS_LDS__GFX09             = 0x00000022,
SQ_PERF_SEL_INSTS_GDS__GFX09             = 0x00000023,
SQ_PERF_SEL_INSTS_EXP__GFX09             = 0x00000024,
SQ_PERF_SEL_INSTS_EXP_GDS__GFX09         = 0x00000025,
SQ_PERF_SEL_INSTS_BRANCH__GFX09          = 0x00000026,
SQ_PERF_SEL_INSTS_SENDMSG__GFX09         = 0x00000027,
SQ_PERF_SEL_INSTS_VSKIPPED__GFX09        = 0x00000028,
SQ_PERF_SEL_INST_LEVEL_VMEM__GFX09       = 0x00000029,
SQ_PERF_SEL_INST_LEVEL_SMEM__GFX09       = 0x0000002a,
SQ_PERF_SEL_INST_LEVEL_LDS__GFX09        = 0x0000002b,
SQ_PERF_SEL_INST_LEVEL_GDS__GFX09        = 0x0000002c,
SQ_PERF_SEL_INST_LEVEL_EXP__GFX09        = 0x0000002d,
SQ_PERF_SEL_WAVE_CYCLES__GFX09           = 0x0000002e,
SQ_PERF_SEL_WAVE_READY__GFX09            = 0x0000002f,
SQ_PERF_SEL_WAIT_CNT_VM__GFX09           = 0x00000030,
SQ_PERF_SEL_WAIT_CNT_LGKM__GFX09         = 0x00000031,
SQ_PERF_SEL_WAIT_CNT_EXP__GFX09          = 0x00000032,
SQ_PERF_SEL_WAIT_CNT_ANY__GFX09          = 0x00000033,
SQ_PERF_SEL_WAIT_BARRIER__GFX09          = 0x00000034,
SQ_PERF_SEL_WAIT_EXP_ALLOC__GFX09        = 0x00000035,
SQ_PERF_SEL_WAIT_SLEEP__GFX09            = 0x00000036,
SQ_PERF_SEL_WAIT_OTHER__GFX09            = 0x00000038,
SQ_PERF_SEL_WAIT_ANY__GFX09              = 0x00000039,
SQ_PERF_SEL_WAIT_TTRACE__GFX09           = 0x0000003a,
SQ_PERF_SEL_WAIT_IFETCH__GFX09           = 0x0000003b,
SQ_PERF_SEL_WAIT_INST_VMEM__GFX09        = 0x0000003d,
SQ_PERF_SEL_WAIT_INST_SCA__GFX09         = 0x0000003e,
SQ_PERF_SEL_WAIT_INST_LDS__GFX09         = 0x0000003f,
SQ_PERF_SEL_WAIT_INST_VALU__GFX09        = 0x00000040,
SQ_PERF_SEL_WAIT_INST_EXP_GDS__GFX09     = 0x00000041,
SQ_PERF_SEL_WAIT_INST_MISC__GFX09        = 0x00000042,
SQ_PERF_SEL_WAIT_INST_FLAT__GFX09        = 0x00000043,
SQ_PERF_SEL_ACTIVE_INST_ANY__GFX09       = 0x00000044,
SQ_PERF_SEL_ACTIVE_INST_VMEM__GFX09      = 0x00000045,
SQ_PERF_SEL_ACTIVE_INST_LDS__GFX09       = 0x00000046,
SQ_PERF_SEL_ACTIVE_INST_VALU__GFX09      = 0x00000047,
SQ_PERF_SEL_ACTIVE_INST_SCA__GFX09       = 0x00000048,
SQ_PERF_SEL_ACTIVE_INST_EXP_GDS__GFX09   = 0x00000049,
SQ_PERF_SEL_ACTIVE_INST_MISC__GFX09      = 0x0000004a,
SQ_PERF_SEL_ACTIVE_INST_FLAT__GFX09      = 0x0000004b,
SQ_PERF_SEL_INST_CYCLES_VMEM_WR__GFX09   = 0x0000004c,
SQ_PERF_SEL_INST_CYCLES_VMEM_RD__GFX09   = 0x0000004d,
SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR__GFX09 = 0x0000004e,
SQ_PERF_SEL_INST_CYCLES_VMEM_DATA__GFX09 = 0x0000004f,
SQ_PERF_SEL_INST_CYCLES_VMEM_CMD__GFX09  = 0x00000050,
SQ_PERF_SEL_INST_CYCLES_EXP__GFX09       = 0x00000051,
SQ_PERF_SEL_INST_CYCLES_GDS__GFX09       = 0x00000052,
SQ_PERF_SEL_INST_CYCLES_SMEM__GFX09      = 0x00000053,
SQ_PERF_SEL_INST_CYCLES_SALU__GFX09      = 0x00000054,
SQ_PERF_SEL_THREAD_CYCLES_VALU__GFX09    = 0x00000055,
SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX__GFX09 = 0x00000056,
SQ_PERF_SEL_IFETCH__GFX09                = 0x00000057,
SQ_PERF_SEL_IFETCH_LEVEL__GFX09          = 0x00000058,
SQ_PERF_SEL_CBRANCH_FORK__GFX09          = 0x00000059,
SQ_PERF_SEL_CBRANCH_FORK_SPLIT__GFX09    = 0x0000005a,
SQ_PERF_SEL_VALU_LDS_DIRECT_RD__GFX09    = 0x0000005b,
SQ_PERF_SEL_VALU_LDS_INTERP_OP__GFX09    = 0x0000005c,
SQ_PERF_SEL_LDS_BANK_CONFLICT__GFX09     = 0x0000005d,
SQ_PERF_SEL_LDS_ADDR_CONFLICT__GFX09     = 0x0000005e,
SQ_PERF_SEL_LDS_UNALIGNED_STALL__GFX09   = 0x0000005f,
SQ_PERF_SEL_LDS_MEM_VIOLATIONS__GFX09    = 0x00000060,
SQ_PERF_SEL_LDS_ATOMIC_RETURN__GFX09     = 0x00000061,
SQ_PERF_SEL_LDS_IDX_ACTIVE__GFX09        = 0x00000062,
SQ_PERF_SEL_VALU_DEP_STALL__GFX09        = 0x00000063,
SQ_PERF_SEL_VALU_STARVE__GFX09           = 0x00000064,
SQ_PERF_SEL_EXP_REQ_FIFO_FULL__GFX09     = 0x00000066,
SQ_PERF_SEL_LDS_DATA_FIFO_FULL__GFX09    = 0x00000067,
SQ_PERF_SEL_LDS_CMD_FIFO_FULL__GFX09     = 0x00000068,
SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL__GFX09 = 0x00000069,
SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL__GFX09 = 0x0000006a,
SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY__GFX09 = 0x0000006b,
SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL__GFX09 = 0x0000006c,
SQ_PERF_SEL_VALU_SRC_C_CONFLICT__GFX09   = 0x0000006d,
SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT__GFX09 = 0x0000006e,
SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT__GFX09 = 0x0000006f,
SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT__GFX09  = 0x00000070,
SQ_PERF_SEL_LDS_SRC_CD_CONFLICT__GFX09   = 0x00000071,
SQ_PERF_SEL_SRC_CD_BUSY__GFX09           = 0x00000072,
SQ_PERF_SEL_PT_POWER_STALL__GFX09        = 0x00000073,
SQ_PERF_SEL_USER0__GFX09                 = 0x00000074,
SQ_PERF_SEL_USER1__GFX09                 = 0x00000075,
SQ_PERF_SEL_USER2__GFX09                 = 0x00000076,
SQ_PERF_SEL_USER3__GFX09                 = 0x00000077,
SQ_PERF_SEL_USER4__GFX09                 = 0x00000078,
SQ_PERF_SEL_USER5__GFX09                 = 0x00000079,
SQ_PERF_SEL_USER6__GFX09                 = 0x0000007a,
SQ_PERF_SEL_USER7__GFX09                 = 0x0000007b,
SQ_PERF_SEL_USER8__GFX09                 = 0x0000007c,
SQ_PERF_SEL_USER9__GFX09                 = 0x0000007d,
SQ_PERF_SEL_USER10__GFX09                = 0x0000007e,
SQ_PERF_SEL_USER11__GFX09                = 0x0000007f,
SQ_PERF_SEL_USER12__GFX09                = 0x00000080,
SQ_PERF_SEL_USER13__GFX09                = 0x00000081,
SQ_PERF_SEL_USER14__GFX09                = 0x00000082,
SQ_PERF_SEL_USER15__GFX09                = 0x00000083,
SQ_PERF_SEL_USER_LEVEL0__GFX09           = 0x00000084,
SQ_PERF_SEL_USER_LEVEL1__GFX09           = 0x00000085,
SQ_PERF_SEL_USER_LEVEL2__GFX09           = 0x00000086,
SQ_PERF_SEL_USER_LEVEL3__GFX09           = 0x00000087,
SQ_PERF_SEL_USER_LEVEL4__GFX09           = 0x00000088,
SQ_PERF_SEL_USER_LEVEL5__GFX09           = 0x00000089,
SQ_PERF_SEL_USER_LEVEL6__GFX09           = 0x0000008a,
SQ_PERF_SEL_USER_LEVEL7__GFX09           = 0x0000008b,
SQ_PERF_SEL_USER_LEVEL8__GFX09           = 0x0000008c,
SQ_PERF_SEL_USER_LEVEL9__GFX09           = 0x0000008d,
SQ_PERF_SEL_USER_LEVEL10__GFX09          = 0x0000008e,
SQ_PERF_SEL_USER_LEVEL11__GFX09          = 0x0000008f,
SQ_PERF_SEL_USER_LEVEL12__GFX09          = 0x00000090,
SQ_PERF_SEL_USER_LEVEL13__GFX09          = 0x00000091,
SQ_PERF_SEL_USER_LEVEL14__GFX09          = 0x00000092,
SQ_PERF_SEL_USER_LEVEL15__GFX09          = 0x00000093,
SQ_PERF_SEL_POWER_VALU__GFX09            = 0x00000094,
SQ_PERF_SEL_POWER_VALU0__GFX09           = 0x00000095,
SQ_PERF_SEL_POWER_VALU1__GFX09           = 0x00000096,
SQ_PERF_SEL_POWER_VALU2__GFX09           = 0x00000097,
SQ_PERF_SEL_POWER_GPR_RD__GFX09          = 0x00000098,
SQ_PERF_SEL_POWER_GPR_WR__GFX09          = 0x00000099,
SQ_PERF_SEL_POWER_LDS_BUSY__GFX09        = 0x0000009a,
SQ_PERF_SEL_POWER_ALU_BUSY__GFX09        = 0x0000009b,
SQ_PERF_SEL_POWER_TEX_BUSY__GFX09        = 0x0000009c,
SQ_PERF_SEL_ACCUM_PREV_HIRES__GFX09      = 0x0000009d,
SQ_PERF_SEL_WAVES_RESTORED__GFX09        = 0x0000009e,
SQ_PERF_SEL_WAVES_SAVED__GFX09           = 0x0000009f,
SQ_PERF_SEL_INSTS_SMEM_NORM__GFX09       = 0x000000a0,
SQ_PERF_SEL_IFETCH_XNACK__GFX09          = 0x000000a4,
SQ_PERF_SEL_TLB_SHOOTDOWN__GFX09         = 0x000000a5,
SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES__GFX09  = 0x000000a6,
SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY__GFX09  = 0x000000a7,
SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY__GFX09  = 0x000000a8,
SQ_PERF_SEL_INSTS_VMEM_REPLAY__GFX09     = 0x000000a9,
SQ_PERF_SEL_INSTS_SMEM_REPLAY__GFX09     = 0x000000aa,
SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY__GFX09 = 0x000000ab,
SQ_PERF_SEL_INSTS_FLAT_REPLAY__GFX09     = 0x000000ac,
SQ_PERF_SEL_DUMMY_LAST                   = 0x000000ff,
SQC_PERF_SEL_ICACHE_INPUT_VALID_READY__GFX09 = 0x00000100,
SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB__GFX09 = 0x00000101,
SQC_PERF_SEL_ICACHE_INPUT_VALIDB__GFX09  = 0x00000102,
SQC_PERF_SEL_DCACHE_INPUT_VALID_READY__GFX09 = 0x00000103,
SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB__GFX09 = 0x00000104,
SQC_PERF_SEL_DCACHE_INPUT_VALIDB__GFX09  = 0x00000105,
SQC_PERF_SEL_TC_REQ__GFX09               = 0x00000106,
SQC_PERF_SEL_TC_INST_REQ__GFX09          = 0x00000107,
SQC_PERF_SEL_TC_DATA_READ_REQ__GFX09     = 0x00000108,
SQC_PERF_SEL_TC_DATA_WRITE_REQ__GFX09    = 0x00000109,
SQC_PERF_SEL_TC_DATA_ATOMIC_REQ__GFX09   = 0x0000010a,
SQC_PERF_SEL_TC_STALL__GFX09             = 0x0000010b,
SQC_PERF_SEL_TC_STARVE__GFX09            = 0x0000010c,
SQC_PERF_SEL_ICACHE_BUSY_CYCLES__GFX09   = 0x0000010d,
SQC_PERF_SEL_ICACHE_REQ__GFX09           = 0x0000010e,
SQC_PERF_SEL_ICACHE_HITS__GFX09          = 0x0000010f,
SQC_PERF_SEL_ICACHE_MISSES__GFX09        = 0x00000110,
SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE__GFX09 = 0x00000111,
SQC_PERF_SEL_ICACHE_INVAL_INST__GFX09    = 0x00000112,
SQC_PERF_SEL_ICACHE_INVAL_ASYNC__GFX09   = 0x00000113,
SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT__GFX09 = 0x00000114,
SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB__GFX09 = 0x00000115,
SQC_PERF_SEL_ICACHE_CACHE_STALLED__GFX09 = 0x00000116,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO__GFX09 = 0x00000117,
SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX__GFX09 = 0x00000118,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT__GFX09 = 0x00000119,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO__GFX09 = 0x0000011a,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO__GFX09 = 0x0000011b,
SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF__GFX09 = 0x0000011c,
SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT__GFX09 = 0x0000011d,
SQC_PERF_SEL_DCACHE_BUSY_CYCLES__GFX09   = 0x00000121,
SQC_PERF_SEL_DCACHE_REQ__GFX09           = 0x00000122,
SQC_PERF_SEL_DCACHE_HITS__GFX09          = 0x00000123,
SQC_PERF_SEL_DCACHE_MISSES__GFX09        = 0x00000124,
SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE__GFX09 = 0x00000125,
SQC_PERF_SEL_DCACHE_HIT_LRU_READ__GFX09  = 0x00000126,
SQC_PERF_SEL_DCACHE_MISS_EVICT_READ__GFX09 = 0x00000127,
SQC_PERF_SEL_DCACHE_WC_LRU_WRITE__GFX09  = 0x00000128,
SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE__GFX09 = 0x00000129,
SQC_PERF_SEL_DCACHE_ATOMIC__GFX09        = 0x0000012a,
SQC_PERF_SEL_DCACHE_VOLATILE__GFX09      = 0x0000012b,
SQC_PERF_SEL_DCACHE_INVAL_INST__GFX09    = 0x0000012c,
SQC_PERF_SEL_DCACHE_INVAL_ASYNC__GFX09   = 0x0000012d,
SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST__GFX09 = 0x0000012e,
SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC__GFX09 = 0x0000012f,
SQC_PERF_SEL_DCACHE_WB_INST__GFX09       = 0x00000130,
SQC_PERF_SEL_DCACHE_WB_ASYNC__GFX09      = 0x00000131,
SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST__GFX09 = 0x00000132,
SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC__GFX09 = 0x00000133,
SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT__GFX09 = 0x00000134,
SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB__GFX09 = 0x00000135,
SQC_PERF_SEL_DCACHE_CACHE_STALLED__GFX09 = 0x00000136,
SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX__GFX09 = 0x00000137,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT__GFX09 = 0x00000138,
SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT__GFX09 = 0x00000139,
SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED__GFX09 = 0x0000013a,
SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE__GFX09 = 0x0000013b,
SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT__GFX09 = 0x0000013c,
SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH__GFX09 = 0x0000013d,
SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE__GFX09 = 0x0000013e,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO__GFX09 = 0x0000013f,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO__GFX09 = 0x00000140,
SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF__GFX09 = 0x00000141,
SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT__GFX09 = 0x00000142,
SQC_PERF_SEL_DCACHE_REQ_READ_1__GFX09    = 0x00000143,
SQC_PERF_SEL_DCACHE_REQ_READ_2__GFX09    = 0x00000144,
SQC_PERF_SEL_DCACHE_REQ_READ_4__GFX09    = 0x00000145,
SQC_PERF_SEL_DCACHE_REQ_READ_8__GFX09    = 0x00000146,
SQC_PERF_SEL_DCACHE_REQ_READ_16__GFX09   = 0x00000147,
SQC_PERF_SEL_DCACHE_REQ_TIME__GFX09      = 0x00000148,
SQC_PERF_SEL_DCACHE_REQ_WRITE_1__GFX09   = 0x00000149,
SQC_PERF_SEL_DCACHE_REQ_WRITE_2__GFX09   = 0x0000014a,
SQC_PERF_SEL_DCACHE_REQ_WRITE_4__GFX09   = 0x0000014b,
SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE__GFX09 = 0x0000014c,
SQC_PERF_SEL_SQ_DCACHE_REQS__GFX09       = 0x0000014d,
SQC_PERF_SEL_DCACHE_FLAT_REQ__GFX09      = 0x0000014e,
SQC_PERF_SEL_DCACHE_NONFLAT_REQ__GFX09   = 0x0000014f,
SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL__GFX09 = 0x00000150,
SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL__GFX09 = 0x00000151,
SQC_PERF_SEL_TC_INFLIGHT_LEVEL__GFX09    = 0x00000152,
SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL__GFX09 = 0x00000153,
SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL__GFX09 = 0x00000154,
SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS__GFX09 = 0x00000155,
SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS__GFX09 = 0x00000156,
SQC_PERF_SEL_ICACHE_GATCL1_REQUEST__GFX09 = 0x00000158,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX__GFX09 = 0x00000159,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT__GFX09 = 0x0000015a,
SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL__GFX09 = 0x0000015b,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES__GFX09 = 0x0000015c,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS__GFX09 = 0x0000015d,
SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT__GFX09 = 0x0000015e,
SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL__GFX09 = 0x0000015f,
SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS__GFX09 = 0x00000160,
SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS__GFX09 = 0x00000161,
SQC_PERF_SEL_DCACHE_GATCL1_REQUEST__GFX09 = 0x00000163,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX__GFX09 = 0x00000164,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT__GFX09 = 0x00000165,
SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL__GFX09 = 0x00000166,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES__GFX09 = 0x00000167,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS__GFX09 = 0x00000168,
SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT__GFX09 = 0x00000169,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL__GFX09 = 0x0000016a,
SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS__GFX09 = 0x0000016b,
SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL__GFX09 = 0x0000016c,
SQC_PERF_SEL_DUMMY_LAST__GFX09           = 0x00000175,
} SQ_PERF_SEL;

typedef enum SQ_ROUND_MODE {
SQ_ROUND_NEAREST_EVEN                    = 0x00000000,
SQ_ROUND_PLUS_INFINITY                   = 0x00000001,
SQ_ROUND_MINUS_INFINITY                  = 0x00000002,
SQ_ROUND_TO_ZERO                         = 0x00000003,
} SQ_ROUND_MODE;

typedef enum SQ_RSRC_BUF_TYPE {
SQ_RSRC_BUF                              = 0x00000000,
SQ_RSRC_BUF_RSVD_1                       = 0x00000001,
SQ_RSRC_BUF_RSVD_2                       = 0x00000002,
SQ_RSRC_BUF_RSVD_3                       = 0x00000003,
} SQ_RSRC_BUF_TYPE;

typedef enum SQ_RSRC_FLAT_TYPE {
SQ_RSRC_FLAT_RSVD_0                      = 0x00000000,
SQ_RSRC_FLAT                             = 0x00000001,
SQ_RSRC_FLAT_RSVD_2                      = 0x00000002,
SQ_RSRC_FLAT_RSVD_3                      = 0x00000003,
} SQ_RSRC_FLAT_TYPE;

typedef enum SQ_RSRC_IMG_TYPE {
SQ_RSRC_IMG_RSVD_0                       = 0x00000000,
SQ_RSRC_IMG_RSVD_1                       = 0x00000001,
SQ_RSRC_IMG_RSVD_2                       = 0x00000002,
SQ_RSRC_IMG_RSVD_3                       = 0x00000003,
SQ_RSRC_IMG_RSVD_4                       = 0x00000004,
SQ_RSRC_IMG_RSVD_5                       = 0x00000005,
SQ_RSRC_IMG_RSVD_6                       = 0x00000006,
SQ_RSRC_IMG_RSVD_7                       = 0x00000007,
SQ_RSRC_IMG_1D                           = 0x00000008,
SQ_RSRC_IMG_2D                           = 0x00000009,
SQ_RSRC_IMG_3D                           = 0x0000000a,
SQ_RSRC_IMG_CUBE                         = 0x0000000b,
SQ_RSRC_IMG_1D_ARRAY                     = 0x0000000c,
SQ_RSRC_IMG_2D_ARRAY                     = 0x0000000d,
SQ_RSRC_IMG_2D_MSAA                      = 0x0000000e,
SQ_RSRC_IMG_2D_MSAA_ARRAY                = 0x0000000f,
} SQ_RSRC_IMG_TYPE;

typedef enum SQ_SEL_XYZW01 {
SQ_SEL_0                                 = 0x00000000,
SQ_SEL_1                                 = 0x00000001,
SQ_SEL_RESERVED_1                        = 0x00000003,
SQ_SEL_X                                 = 0x00000004,
SQ_SEL_Y                                 = 0x00000005,
SQ_SEL_Z                                 = 0x00000006,
SQ_SEL_W                                 = 0x00000007,
} SQ_SEL_XYZW01;

typedef enum SQ_TEX_ANISO_RATIO {
SQ_TEX_ANISO_RATIO_1                     = 0x00000000,
SQ_TEX_ANISO_RATIO_2                     = 0x00000001,
SQ_TEX_ANISO_RATIO_4                     = 0x00000002,
SQ_TEX_ANISO_RATIO_8                     = 0x00000003,
SQ_TEX_ANISO_RATIO_16                    = 0x00000004,
} SQ_TEX_ANISO_RATIO;

typedef enum SQ_TEX_BORDER_COLOR {
SQ_TEX_BORDER_COLOR_TRANS_BLACK          = 0x00000000,
SQ_TEX_BORDER_COLOR_OPAQUE_BLACK         = 0x00000001,
SQ_TEX_BORDER_COLOR_OPAQUE_WHITE         = 0x00000002,
SQ_TEX_BORDER_COLOR_REGISTER             = 0x00000003,
} SQ_TEX_BORDER_COLOR;

typedef enum SQ_TEX_CLAMP {
SQ_TEX_WRAP                              = 0x00000000,
SQ_TEX_MIRROR                            = 0x00000001,
SQ_TEX_CLAMP_LAST_TEXEL                  = 0x00000002,
SQ_TEX_MIRROR_ONCE_LAST_TEXEL            = 0x00000003,
SQ_TEX_CLAMP_HALF_BORDER                 = 0x00000004,
SQ_TEX_MIRROR_ONCE_HALF_BORDER           = 0x00000005,
SQ_TEX_CLAMP_BORDER                      = 0x00000006,
SQ_TEX_MIRROR_ONCE_BORDER                = 0x00000007,
} SQ_TEX_CLAMP;

typedef enum SQ_TEX_DEPTH_COMPARE {
SQ_TEX_DEPTH_COMPARE_NEVER               = 0x00000000,
SQ_TEX_DEPTH_COMPARE_LESS                = 0x00000001,
SQ_TEX_DEPTH_COMPARE_EQUAL               = 0x00000002,
SQ_TEX_DEPTH_COMPARE_LESSEQUAL           = 0x00000003,
SQ_TEX_DEPTH_COMPARE_GREATER             = 0x00000004,
SQ_TEX_DEPTH_COMPARE_NOTEQUAL            = 0x00000005,
SQ_TEX_DEPTH_COMPARE_GREATEREQUAL        = 0x00000006,
SQ_TEX_DEPTH_COMPARE_ALWAYS              = 0x00000007,
} SQ_TEX_DEPTH_COMPARE;

typedef enum SQ_TEX_MIP_FILTER {
SQ_TEX_MIP_FILTER_NONE                   = 0x00000000,
SQ_TEX_MIP_FILTER_POINT                  = 0x00000001,
SQ_TEX_MIP_FILTER_LINEAR                 = 0x00000002,
SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ        = 0x00000003,
} SQ_TEX_MIP_FILTER;

typedef enum SQ_TEX_XY_FILTER {
SQ_TEX_XY_FILTER_POINT                   = 0x00000000,
SQ_TEX_XY_FILTER_BILINEAR                = 0x00000001,
SQ_TEX_XY_FILTER_ANISO_POINT             = 0x00000002,
SQ_TEX_XY_FILTER_ANISO_BILINEAR          = 0x00000003,
} SQ_TEX_XY_FILTER;

typedef enum SQ_TEX_Z_FILTER {
SQ_TEX_Z_FILTER_NONE                     = 0x00000000,
SQ_TEX_Z_FILTER_POINT                    = 0x00000001,
SQ_TEX_Z_FILTER_LINEAR                   = 0x00000002,
} SQ_TEX_Z_FILTER;

typedef enum SQ_THREAD_TRACE_CAPTURE_MODE {
SQ_THREAD_TRACE_CAPTURE_MODE_ALL         = 0x00000000,
SQ_THREAD_TRACE_CAPTURE_MODE_SELECT      = 0x00000001,
SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x00000002,
} SQ_THREAD_TRACE_CAPTURE_MODE;

typedef enum SQ_THREAD_TRACE_INST_TYPE {
SQ_THREAD_TRACE_INST_TYPE_SMEM_RD        = 0x00000000,
SQ_THREAD_TRACE_INST_TYPE_SALU_32        = 0x00000001,
SQ_THREAD_TRACE_INST_TYPE_VMEM_RD        = 0x00000002,
SQ_THREAD_TRACE_INST_TYPE_VMEM_WR        = 0x00000003,
SQ_THREAD_TRACE_INST_TYPE_FLAT_WR        = 0x00000004,
SQ_THREAD_TRACE_INST_TYPE_VALU_32        = 0x00000005,
SQ_THREAD_TRACE_INST_TYPE_LDS            = 0x00000006,
SQ_THREAD_TRACE_INST_TYPE_PC             = 0x00000007,
SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS     = 0x00000008,
SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX     = 0x00000009,
SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0x0000000a,
SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0x0000000b,
SQ_THREAD_TRACE_INST_TYPE_JUMP           = 0x0000000c,
SQ_THREAD_TRACE_INST_TYPE_NEXT           = 0x0000000d,
SQ_THREAD_TRACE_INST_TYPE_FLAT_RD        = 0x0000000e,
SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG      = 0x0000000f,
SQ_THREAD_TRACE_INST_TYPE_SMEM_WR        = 0x00000010,
SQ_THREAD_TRACE_INST_TYPE_SALU_64        = 0x00000011,
SQ_THREAD_TRACE_INST_TYPE_VALU_64        = 0x00000012,
SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x00000013,
SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x00000014,
SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x00000015,
SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x00000016,
SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x00000017,
SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x00000018,
} SQ_THREAD_TRACE_INST_TYPE;

typedef enum SQ_THREAD_TRACE_ISSUE {
SQ_THREAD_TRACE_ISSUE_NULL               = 0x00000000,
SQ_THREAD_TRACE_ISSUE_STALL              = 0x00000001,
SQ_THREAD_TRACE_ISSUE_INST               = 0x00000002,
SQ_THREAD_TRACE_ISSUE_IMMED              = 0x00000003,
} SQ_THREAD_TRACE_ISSUE;

typedef enum SQ_THREAD_TRACE_ISSUE_MASK {
SQ_THREAD_TRACE_ISSUE_MASK_ALL           = 0x00000000,
SQ_THREAD_TRACE_ISSUE_MASK_STALLED       = 0x00000001,
SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x00000002,
SQ_THREAD_TRACE_ISSUE_MASK_IMMED         = 0x00000003,
} SQ_THREAD_TRACE_ISSUE_MASK;

typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE {
SQ_THREAD_TRACE_MISC_TOKEN_TIME          = 0x00000000,
SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET    = 0x00000001,
SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST   = 0x00000002,
SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC     = 0x00000003,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x00000004,
SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x00000005,
SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX       = 0x00000006,
SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN    = 0x00000007,
} SQ_THREAD_TRACE_MISC_TOKEN_TYPE;

typedef enum SQ_THREAD_TRACE_MODE_SEL {
SQ_THREAD_TRACE_MODE_OFF                 = 0x00000000,
SQ_THREAD_TRACE_MODE_ON                  = 0x00000001,
} SQ_THREAD_TRACE_MODE_SEL;

typedef enum SQ_THREAD_TRACE_REG_OP {
SQ_THREAD_TRACE_REG_OP_READ              = 0x00000000,
SQ_THREAD_TRACE_REG_OP_WRITE             = 0x00000001,
} SQ_THREAD_TRACE_REG_OP;

typedef enum SQ_THREAD_TRACE_REG_TYPE {
SQ_THREAD_TRACE_REG_TYPE_EVENT           = 0x00000000,
SQ_THREAD_TRACE_REG_TYPE_DRAW            = 0x00000001,
SQ_THREAD_TRACE_REG_TYPE_DISPATCH        = 0x00000002,
SQ_THREAD_TRACE_REG_TYPE_USERDATA        = 0x00000003,
SQ_THREAD_TRACE_REG_TYPE_MARKER          = 0x00000004,
SQ_THREAD_TRACE_REG_TYPE_GFXDEC          = 0x00000005,
SQ_THREAD_TRACE_REG_TYPE_SHDEC           = 0x00000006,
SQ_THREAD_TRACE_REG_TYPE_OTHER           = 0x00000007,
} SQ_THREAD_TRACE_REG_TYPE;

typedef enum SQ_THREAD_TRACE_TOKEN_TYPE {
SQ_THREAD_TRACE_TOKEN_MISC               = 0x00000000,
SQ_THREAD_TRACE_TOKEN_TIMESTAMP          = 0x00000001,
SQ_THREAD_TRACE_TOKEN_REG                = 0x00000002,
SQ_THREAD_TRACE_TOKEN_WAVE_START         = 0x00000003,
SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC         = 0x00000004,
SQ_THREAD_TRACE_TOKEN_REG_CSPRIV         = 0x00000005,
SQ_THREAD_TRACE_TOKEN_WAVE_END           = 0x00000006,
SQ_THREAD_TRACE_TOKEN_EVENT              = 0x00000007,
SQ_THREAD_TRACE_TOKEN_EVENT_CS           = 0x00000008,
SQ_THREAD_TRACE_TOKEN_EVENT_GFX1         = 0x00000009,
SQ_THREAD_TRACE_TOKEN_INST               = 0x0000000a,
SQ_THREAD_TRACE_TOKEN_INST_PC            = 0x0000000b,
SQ_THREAD_TRACE_TOKEN_INST_USERDATA      = 0x0000000c,
SQ_THREAD_TRACE_TOKEN_ISSUE              = 0x0000000d,
SQ_THREAD_TRACE_TOKEN_PERF               = 0x0000000e,
SQ_THREAD_TRACE_TOKEN_REG_CS             = 0x0000000f,
} SQ_THREAD_TRACE_TOKEN_TYPE;

typedef enum SQ_THREAD_TRACE_VM_ID_MASK {
SQ_THREAD_TRACE_VM_ID_MASK_SINGLE        = 0x00000000,
SQ_THREAD_TRACE_VM_ID_MASK_ALL           = 0x00000001,
SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x00000002,
} SQ_THREAD_TRACE_VM_ID_MASK;

typedef enum SQ_THREAD_TRACE_WAVE_MASK {
SQ_THREAD_TRACE_WAVE_MASK_NONE           = 0x00000000,
SQ_THREAD_TRACE_WAVE_MASK_ALL            = 0x00000001,
} SQ_THREAD_TRACE_WAVE_MASK;

typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX {
SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x00000018,
SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x00000019,
} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX;

typedef enum SQ_WAVE_IB_ECC_ST {
SQ_WAVE_IB_ECC_CLEAN                     = 0x00000000,
SQ_WAVE_IB_ECC_ERR_CONTINUE              = 0x00000001,
SQ_WAVE_IB_ECC_ERR_HALT                  = 0x00000002,
SQ_WAVE_IB_ECC_WITH_ERR_MSG              = 0x00000003,
} SQ_WAVE_IB_ECC_ST;

typedef enum SQ_WAVE_TYPE {
SQ_WAVE_TYPE_PS                          = 0x00000000,
SQ_WAVE_TYPE_VS                          = 0x00000001,
SQ_WAVE_TYPE_GS                          = 0x00000002,
SQ_WAVE_TYPE_ES                          = 0x00000003,
SQ_WAVE_TYPE_HS                          = 0x00000004,
SQ_WAVE_TYPE_LS                          = 0x00000005,
SQ_WAVE_TYPE_CS                          = 0x00000006,
SQ_WAVE_TYPE_PS1                         = 0x00000007,
} SQ_WAVE_TYPE;

typedef enum SU_PERFCNT_SEL {
PERF_PAPC_PASX_REQ                       = 0x00000000,
PERF_PAPC_PASX_DISABLE_PIPE              = 0x00000001,
PERF_PAPC_PASX_FIRST_VECTOR              = 0x00000002,
PERF_PAPC_PASX_SECOND_VECTOR             = 0x00000003,
PERF_PAPC_PASX_FIRST_DEAD                = 0x00000004,
PERF_PAPC_PASX_SECOND_DEAD               = 0x00000005,
PERF_PAPC_PASX_VTX_KILL_DISCARD          = 0x00000006,
PERF_PAPC_PASX_VTX_NAN_DISCARD           = 0x00000007,
PERF_PAPC_PA_INPUT_PRIM                  = 0x00000008,
PERF_PAPC_PA_INPUT_NULL_PRIM             = 0x00000009,
PERF_PAPC_PA_INPUT_EVENT_FLAG            = 0x0000000a,
PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT       = 0x0000000b,
PERF_PAPC_PA_INPUT_END_OF_PACKET         = 0x0000000c,
PERF_PAPC_PA_INPUT_EXTENDED_EVENT        = 0x0000000d,
PERF_PAPC_CLPR_CULL_PRIM                 = 0x0000000e,
PERF_PAPC_CLPR_VVUCP_CULL_PRIM           = 0x0000000f,
PERF_PAPC_CLPR_VV_CULL_PRIM              = 0x00000010,
PERF_PAPC_CLPR_UCP_CULL_PRIM             = 0x00000011,
PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM        = 0x00000012,
PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM         = 0x00000013,
PERF_PAPC_CLPR_CULL_TO_NULL_PRIM         = 0x00000014,
PERF_PAPC_CLPR_VVUCP_CLIP_PRIM           = 0x00000015,
PERF_PAPC_CLPR_VV_CLIP_PRIM              = 0x00000016,
PERF_PAPC_CLPR_UCP_CLIP_PRIM             = 0x00000017,
PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE      = 0x00000018,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_1          = 0x00000019,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_2          = 0x0000001a,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_3          = 0x0000001b,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_4          = 0x0000001c,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8        = 0x0000001d,
PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12       = 0x0000001e,
PERF_PAPC_CLPR_CLIP_PLANE_NEAR           = 0x0000001f,
PERF_PAPC_CLPR_CLIP_PLANE_FAR            = 0x00000020,
PERF_PAPC_CLPR_CLIP_PLANE_LEFT           = 0x00000021,
PERF_PAPC_CLPR_CLIP_PLANE_RIGHT          = 0x00000022,
PERF_PAPC_CLPR_CLIP_PLANE_TOP            = 0x00000023,
PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM         = 0x00000024,
PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM        = 0x00000025,
PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM     = 0x00000026,
PERF_PAPC_CLSM_NULL_PRIM                 = 0x00000027,
PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM      = 0x00000028,
PERF_PAPC_CLSM_CULL_TO_NULL_PRIM         = 0x00000029,
PERF_PAPC_CLSM_OUT_PRIM_CNT_1            = 0x0000002a,
PERF_PAPC_CLSM_OUT_PRIM_CNT_2            = 0x0000002b,
PERF_PAPC_CLSM_OUT_PRIM_CNT_3            = 0x0000002c,
PERF_PAPC_CLSM_OUT_PRIM_CNT_4            = 0x0000002d,
PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8          = 0x0000002e,
PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13         = 0x0000002f,
PERF_PAPC_CLIPGA_VTE_KILL_PRIM           = 0x00000030,
PERF_PAPC_SU_INPUT_PRIM                  = 0x00000031,
PERF_PAPC_SU_INPUT_CLIP_PRIM             = 0x00000032,
PERF_PAPC_SU_INPUT_NULL_PRIM             = 0x00000033,
PERF_PAPC_SU_INPUT_PRIM_DUAL             = 0x00000034,
PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL        = 0x00000035,
PERF_PAPC_SU_ZERO_AREA_CULL_PRIM         = 0x00000036,
PERF_PAPC_SU_BACK_FACE_CULL_PRIM         = 0x00000037,
PERF_PAPC_SU_FRONT_FACE_CULL_PRIM        = 0x00000038,
PERF_PAPC_SU_POLYMODE_FACE_CULL          = 0x00000039,
PERF_PAPC_SU_POLYMODE_BACK_CULL          = 0x0000003a,
PERF_PAPC_SU_POLYMODE_FRONT_CULL         = 0x0000003b,
PERF_PAPC_SU_POLYMODE_INVALID_FILL       = 0x0000003c,
PERF_PAPC_SU_OUTPUT_PRIM                 = 0x0000003d,
PERF_PAPC_SU_OUTPUT_CLIP_PRIM            = 0x0000003e,
PERF_PAPC_SU_OUTPUT_NULL_PRIM            = 0x0000003f,
PERF_PAPC_SU_OUTPUT_EVENT_FLAG           = 0x00000040,
PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT      = 0x00000041,
PERF_PAPC_SU_OUTPUT_END_OF_PACKET        = 0x00000042,
PERF_PAPC_SU_OUTPUT_POLYMODE_FACE        = 0x00000043,
PERF_PAPC_SU_OUTPUT_POLYMODE_BACK        = 0x00000044,
PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT       = 0x00000045,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE      = 0x00000046,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK      = 0x00000047,
PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT     = 0x00000048,
PERF_PAPC_SU_OUTPUT_PRIM_DUAL            = 0x00000049,
PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL       = 0x0000004a,
PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL        = 0x0000004b,
PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL   = 0x0000004c,
PERF_PAPC_PASX_REQ_IDLE                  = 0x0000004d,
PERF_PAPC_PASX_REQ_BUSY                  = 0x0000004e,
PERF_PAPC_PASX_REQ_STALLED               = 0x0000004f,
PERF_PAPC_PASX_REC_IDLE                  = 0x00000050,
PERF_PAPC_PASX_REC_BUSY                  = 0x00000051,
PERF_PAPC_PASX_REC_STARVED_SX            = 0x00000052,
PERF_PAPC_PASX_REC_STALLED               = 0x00000053,
PERF_PAPC_PASX_REC_STALLED_POS_MEM       = 0x00000054,
PERF_PAPC_PASX_REC_STALLED_CCGSM_IN      = 0x00000055,
PERF_PAPC_CCGSM_IDLE                     = 0x00000056,
PERF_PAPC_CCGSM_BUSY                     = 0x00000057,
PERF_PAPC_CCGSM_STALLED                  = 0x00000058,
PERF_PAPC_CLPRIM_IDLE                    = 0x00000059,
PERF_PAPC_CLPRIM_BUSY                    = 0x0000005a,
PERF_PAPC_CLPRIM_STALLED                 = 0x0000005b,
PERF_PAPC_CLPRIM_STARVED_CCGSM           = 0x0000005c,
PERF_PAPC_CLIPSM_IDLE                    = 0x0000005d,
PERF_PAPC_CLIPSM_BUSY                    = 0x0000005e,
PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH     = 0x0000005f,
PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ       = 0x00000060,
PERF_PAPC_CLIPSM_WAIT_CLIPGA             = 0x00000061,
PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP     = 0x00000062,
PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM         = 0x00000063,
PERF_PAPC_CLIPGA_IDLE                    = 0x00000064,
PERF_PAPC_CLIPGA_BUSY                    = 0x00000065,
PERF_PAPC_CLIPGA_STARVED_VTE_CLIP        = 0x00000066,
PERF_PAPC_CLIPGA_STALLED                 = 0x00000067,
PERF_PAPC_CLIP_IDLE                      = 0x00000068,
PERF_PAPC_CLIP_BUSY                      = 0x00000069,
PERF_PAPC_SU_IDLE                        = 0x0000006a,
PERF_PAPC_SU_BUSY                        = 0x0000006b,
PERF_PAPC_SU_STARVED_CLIP                = 0x0000006c,
PERF_PAPC_SU_STALLED_SC                  = 0x0000006d,
PERF_PAPC_CL_DYN_SCLK_VLD                = 0x0000006e,
PERF_PAPC_SU_DYN_SCLK_VLD                = 0x0000006f,
PERF_PAPC_PA_REG_SCLK_VLD                = 0x00000070,
PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL  = 0x00000071,
PERF_PAPC_PASX_SE0_REQ                   = 0x00000072,
PERF_PAPC_PASX_SE1_REQ                   = 0x00000073,
PERF_PAPC_PASX_SE0_FIRST_VECTOR          = 0x00000074,
PERF_PAPC_PASX_SE0_SECOND_VECTOR         = 0x00000075,
PERF_PAPC_PASX_SE1_FIRST_VECTOR          = 0x00000076,
PERF_PAPC_PASX_SE1_SECOND_VECTOR         = 0x00000077,
PERF_PAPC_SU_SE0_PRIM_FILTER_CULL        = 0x00000078,
PERF_PAPC_SU_SE1_PRIM_FILTER_CULL        = 0x00000079,
PERF_PAPC_SU_SE01_PRIM_FILTER_CULL       = 0x0000007a,
PERF_PAPC_SU_SE0_OUTPUT_PRIM             = 0x0000007b,
PERF_PAPC_SU_SE1_OUTPUT_PRIM             = 0x0000007c,
PERF_PAPC_SU_SE01_OUTPUT_PRIM            = 0x0000007d,
PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM        = 0x0000007e,
PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM        = 0x0000007f,
PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM       = 0x00000080,
PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT  = 0x00000081,
PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT  = 0x00000082,
PERF_PAPC_SU_SE0_STALLED_SC              = 0x00000083,
PERF_PAPC_SU_SE1_STALLED_SC              = 0x00000084,
PERF_PAPC_SU_SE01_STALLED_SC             = 0x00000085,
PERF_PAPC_CLSM_CLIPPING_PRIM             = 0x00000086,
PERF_PAPC_SU_CULLED_PRIM                 = 0x00000087,
PERF_PAPC_SU_OUTPUT_EOPG                 = 0x00000088,
PERF_PAPC_SU_SE2_PRIM_FILTER_CULL        = 0x00000089,
PERF_PAPC_SU_SE3_PRIM_FILTER_CULL        = 0x0000008a,
PERF_PAPC_SU_SE2_OUTPUT_PRIM             = 0x0000008b,
PERF_PAPC_SU_SE3_OUTPUT_PRIM             = 0x0000008c,
PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM        = 0x0000008d,
PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM        = 0x0000008e,
PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET    = 0x0000008f,
PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET    = 0x00000090,
PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET    = 0x00000091,
PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET    = 0x00000092,
PERF_PAPC_SU_SE0_OUTPUT_EOPG             = 0x00000093,
PERF_PAPC_SU_SE1_OUTPUT_EOPG             = 0x00000094,
PERF_PAPC_SU_SE2_OUTPUT_EOPG             = 0x00000095,
PERF_PAPC_SU_SE3_OUTPUT_EOPG             = 0x00000096,
PERF_PAPC_SU_SE2_STALLED_SC              = 0x00000097,
PERF_PAPC_SU_SE3_STALLED_SC              = 0x00000098,
PERF_CLIENT_UTCL1_INFLIGHT__GFX09        = 0x00000123,
} SU_PERFCNT_SEL;

typedef enum SWIZZLE_MODE_ENUM {
SW_LINEAR                                = 0x00000000,
SW_256B_S                                = 0x00000001,
SW_256B_D                                = 0x00000002,
SW_256B_R                                = 0x00000003,
SW_4KB_Z                                 = 0x00000004,
SW_4KB_S                                 = 0x00000005,
SW_4KB_D                                 = 0x00000006,
SW_4KB_R                                 = 0x00000007,
SW_64KB_Z                                = 0x00000008,
SW_64KB_S                                = 0x00000009,
SW_64KB_D                                = 0x0000000a,
SW_64KB_R                                = 0x0000000b,
SW_VAR_Z                                 = 0x0000000c,
SW_VAR_S                                 = 0x0000000d,
SW_VAR_D                                 = 0x0000000e,
SW_VAR_R                                 = 0x0000000f,
SW_64KB_Z_T                              = 0x00000010,
SW_64KB_S_T                              = 0x00000011,
SW_64KB_D_T                              = 0x00000012,
SW_64KB_R_T                              = 0x00000013,
SW_4KB_Z_X                               = 0x00000014,
SW_4KB_S_X                               = 0x00000015,
SW_4KB_D_X                               = 0x00000016,
SW_4KB_R_X                               = 0x00000017,
SW_64KB_Z_X                              = 0x00000018,
SW_64KB_S_X                              = 0x00000019,
SW_64KB_D_X                              = 0x0000001a,
SW_64KB_R_X                              = 0x0000001b,
SW_VAR_Z_X                               = 0x0000001c,
SW_VAR_S_X                               = 0x0000001d,
SW_VAR_D_X                               = 0x0000001e,
SW_VAR_R_X                               = 0x0000001f,
} SWIZZLE_MODE_ENUM;

typedef enum SWIZZLE_TYPE_ENUM {
SW_Z                                     = 0x00000000,
SW_S                                     = 0x00000001,
SW_D                                     = 0x00000002,
SW_R                                     = 0x00000003,
SW_L                                     = 0x00000004,
} SWIZZLE_TYPE_ENUM;

typedef enum SX_BLEND_OPT {
BLEND_OPT_PRESERVE_NONE_IGNORE_ALL       = 0x00000000,
BLEND_OPT_PRESERVE_ALL_IGNORE_NONE       = 0x00000001,
BLEND_OPT_PRESERVE_C1_IGNORE_C0          = 0x00000002,
BLEND_OPT_PRESERVE_C0_IGNORE_C1          = 0x00000003,
BLEND_OPT_PRESERVE_A1_IGNORE_A0          = 0x00000004,
BLEND_OPT_PRESERVE_A0_IGNORE_A1          = 0x00000005,
BLEND_OPT_PRESERVE_NONE_IGNORE_A0        = 0x00000006,
BLEND_OPT_PRESERVE_NONE_IGNORE_NONE      = 0x00000007,
} SX_BLEND_OPT;

typedef enum SX_DOWNCONVERT_FORMAT {
SX_RT_EXPORT_NO_CONVERSION               = 0x00000000,
SX_RT_EXPORT_32_R                        = 0x00000001,
SX_RT_EXPORT_32_A                        = 0x00000002,
SX_RT_EXPORT_10_11_11                    = 0x00000003,
SX_RT_EXPORT_2_10_10_10                  = 0x00000004,
SX_RT_EXPORT_8_8_8_8                     = 0x00000005,
SX_RT_EXPORT_5_6_5                       = 0x00000006,
SX_RT_EXPORT_1_5_5_5                     = 0x00000007,
SX_RT_EXPORT_4_4_4_4                     = 0x00000008,
SX_RT_EXPORT_16_16_GR                    = 0x00000009,
SX_RT_EXPORT_16_16_AR                    = 0x0000000a,
} SX_DOWNCONVERT_FORMAT;

typedef enum SX_OPT_COMB_FCN {
OPT_COMB_NONE                            = 0x00000000,
OPT_COMB_ADD                             = 0x00000001,
OPT_COMB_SUBTRACT                        = 0x00000002,
OPT_COMB_MIN                             = 0x00000003,
OPT_COMB_MAX                             = 0x00000004,
OPT_COMB_REVSUBTRACT                     = 0x00000005,
OPT_COMB_BLEND_DISABLED                  = 0x00000006,
OPT_COMB_SAFE_ADD                        = 0x00000007,
} SX_OPT_COMB_FCN;

typedef enum SX_PERFCOUNTER_VALS {
SX_PERF_SEL_DB3_SIZE                     = 0x000000cf,
} SX_PERFCOUNTER_VALS;

typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
} SampleSplit;

typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT                         = 0x00000000,
CONFIG_2KB_SPLIT                         = 0x00000001,
CONFIG_4KB_SPLIT                         = 0x00000002,
CONFIG_8KB_SPLIT                         = 0x00000003,
} SampleSplitBytes;

typedef enum ScMap {
RASTER_CONFIG_SC_MAP_0                   = 0x00000000,
RASTER_CONFIG_SC_MAP_1                   = 0x00000001,
RASTER_CONFIG_SC_MAP_2                   = 0x00000002,
RASTER_CONFIG_SC_MAP_3                   = 0x00000003,
} ScMap;

typedef enum ScXsel {
RASTER_CONFIG_SC_XSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SC_XSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SC_XSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SC_XSEL_64_WIDE_TILE       = 0x00000003,
} ScXsel;

typedef enum ScYsel {
RASTER_CONFIG_SC_YSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SC_YSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SC_YSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SC_YSEL_64_WIDE_TILE       = 0x00000003,
} ScYsel;

typedef enum SeEnable {
} SeEnable;

typedef enum SeMap {
RASTER_CONFIG_SE_MAP_0                   = 0x00000000,
RASTER_CONFIG_SE_MAP_1                   = 0x00000001,
RASTER_CONFIG_SE_MAP_2                   = 0x00000002,
RASTER_CONFIG_SE_MAP_3                   = 0x00000003,
} SeMap;

typedef enum SePairMap {
RASTER_CONFIG_SE_PAIR_MAP_0              = 0x00000000,
RASTER_CONFIG_SE_PAIR_MAP_1              = 0x00000001,
RASTER_CONFIG_SE_PAIR_MAP_2              = 0x00000002,
RASTER_CONFIG_SE_PAIR_MAP_3              = 0x00000003,
} SePairMap;

typedef enum SePairXsel {
RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE   = 0x00000000,
RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE  = 0x00000001,
RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE  = 0x00000002,
RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE  = 0x00000003,
} SePairXsel;

typedef enum SePairYsel {
RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE   = 0x00000000,
RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE  = 0x00000001,
RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE  = 0x00000002,
RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE  = 0x00000003,
} SePairYsel;

typedef enum SeXsel {
RASTER_CONFIG_SE_XSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SE_XSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SE_XSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SE_XSEL_64_WIDE_TILE       = 0x00000003,
} SeXsel;

typedef enum SeYsel {
RASTER_CONFIG_SE_YSEL_8_WIDE_TILE        = 0x00000000,
RASTER_CONFIG_SE_YSEL_16_WIDE_TILE       = 0x00000001,
RASTER_CONFIG_SE_YSEL_32_WIDE_TILE       = 0x00000002,
RASTER_CONFIG_SE_YSEL_64_WIDE_TILE       = 0x00000003,
} SeYsel;

typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
} ShaderEngineTileSize;

typedef enum SourceFormat {
EXPORT_4C_32BPC                          = 0x00000000,
EXPORT_4C_16BPC                          = 0x00000001,
EXPORT_2C_32BPC_GR                       = 0x00000002,
EXPORT_2C_32BPC_AR                       = 0x00000003,
} SourceFormat;

typedef enum StencilFormat {
STENCIL_INVALID                          = 0x00000000,
STENCIL_8                                = 0x00000001,
} StencilFormat;

typedef enum StencilOp {
STENCIL_KEEP                             = 0x00000000,
STENCIL_ZERO                             = 0x00000001,
STENCIL_ONES                             = 0x00000002,
STENCIL_REPLACE_TEST                     = 0x00000003,
STENCIL_REPLACE_OP                       = 0x00000004,
STENCIL_ADD_CLAMP                        = 0x00000005,
STENCIL_SUB_CLAMP                        = 0x00000006,
STENCIL_INVERT                           = 0x00000007,
STENCIL_ADD_WRAP                         = 0x00000008,
STENCIL_SUB_WRAP                         = 0x00000009,
STENCIL_AND                              = 0x0000000a,
STENCIL_OR                               = 0x0000000b,
STENCIL_XOR                              = 0x0000000c,
STENCIL_NAND                             = 0x0000000d,
STENCIL_NOR                              = 0x0000000e,
STENCIL_XNOR                             = 0x0000000f,
} StencilOp;

typedef enum SurfaceArray {
ARRAY_1D                                 = 0x00000000,
ARRAY_2D                                 = 0x00000001,
ARRAY_3D                                 = 0x00000002,
ARRAY_3D_SLICE                           = 0x00000003,
} SurfaceArray;

typedef enum SurfaceEndian {
ENDIAN_NONE                              = 0x00000000,
ENDIAN_8IN16                             = 0x00000001,
ENDIAN_8IN32                             = 0x00000002,
ENDIAN_8IN64                             = 0x00000003,
} SurfaceEndian;

typedef enum SurfaceFormat {
FMT_INVALID                              = 0x00000000,
FMT_8                                    = 0x00000001,
FMT_16                                   = 0x00000002,
FMT_8_8                                  = 0x00000003,
FMT_32                                   = 0x00000004,
FMT_16_16                                = 0x00000005,
FMT_10_11_11                             = 0x00000006,
FMT_11_11_10                             = 0x00000007,
FMT_10_10_10_2                           = 0x00000008,
FMT_2_10_10_10                           = 0x00000009,
FMT_8_8_8_8                              = 0x0000000a,
FMT_32_32                                = 0x0000000b,
FMT_16_16_16_16                          = 0x0000000c,
FMT_32_32_32                             = 0x0000000d,
FMT_32_32_32_32                          = 0x0000000e,
FMT_RESERVED_4                           = 0x0000000f,
FMT_5_6_5                                = 0x00000010,
FMT_1_5_5_5                              = 0x00000011,
FMT_5_5_5_1                              = 0x00000012,
FMT_4_4_4_4                              = 0x00000013,
FMT_8_24                                 = 0x00000014,
FMT_24_8                                 = 0x00000015,
FMT_X24_8_32_FLOAT                       = 0x00000016,
FMT_RESERVED_33                          = 0x00000017,
FMT_11_11_10_FLOAT                       = 0x00000018,
FMT_16_FLOAT                             = 0x00000019,
FMT_32_FLOAT                             = 0x0000001a,
FMT_16_16_FLOAT                          = 0x0000001b,
FMT_8_24_FLOAT                           = 0x0000001c,
FMT_24_8_FLOAT                           = 0x0000001d,
FMT_32_32_FLOAT                          = 0x0000001e,
FMT_10_11_11_FLOAT                       = 0x0000001f,
FMT_16_16_16_16_FLOAT                    = 0x00000020,
FMT_3_3_2                                = 0x00000021,
FMT_6_5_5                                = 0x00000022,
FMT_32_32_32_32_FLOAT                    = 0x00000023,
FMT_RESERVED_36                          = 0x00000024,
FMT_1                                    = 0x00000025,
FMT_1_REVERSED                           = 0x00000026,
FMT_GB_GR                                = 0x00000027,
FMT_BG_RG                                = 0x00000028,
FMT_32_AS_8                              = 0x00000029,
FMT_32_AS_8_8                            = 0x0000002a,
FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
FMT_8_8_8                                = 0x0000002c,
FMT_16_16_16                             = 0x0000002d,
FMT_16_16_16_FLOAT                       = 0x0000002e,
FMT_4_4                                  = 0x0000002f,
FMT_32_32_32_FLOAT                       = 0x00000030,
FMT_BC1                                  = 0x00000031,
FMT_BC2                                  = 0x00000032,
FMT_BC3                                  = 0x00000033,
FMT_BC4                                  = 0x00000034,
FMT_BC5                                  = 0x00000035,
FMT_BC6                                  = 0x00000036,
FMT_BC7                                  = 0x00000037,
FMT_32_AS_32_32_32_32                    = 0x00000038,
FMT_APC3                                 = 0x00000039,
FMT_APC4                                 = 0x0000003a,
FMT_APC5                                 = 0x0000003b,
FMT_APC6                                 = 0x0000003c,
FMT_APC7                                 = 0x0000003d,
FMT_CTX1                                 = 0x0000003e,
FMT_RESERVED_63                          = 0x0000003f,
} SurfaceFormat;

typedef enum SurfaceNumber {
NUMBER_UNORM                             = 0x00000000,
NUMBER_SNORM                             = 0x00000001,
NUMBER_USCALED                           = 0x00000002,
NUMBER_SSCALED                           = 0x00000003,
NUMBER_UINT                              = 0x00000004,
NUMBER_SINT                              = 0x00000005,
NUMBER_SRGB                              = 0x00000006,
NUMBER_FLOAT                             = 0x00000007,
} SurfaceNumber;

typedef enum SurfaceSwap {
SWAP_STD                                 = 0x00000000,
SWAP_ALT                                 = 0x00000001,
SWAP_STD_REV                             = 0x00000002,
SWAP_ALT_REV                             = 0x00000003,
} SurfaceSwap;

typedef enum SurfaceTiling {
ARRAY_LINEAR                             = 0x00000000,
ARRAY_TILED                              = 0x00000001,
} SurfaceTiling;

typedef enum TA_PERFCOUNT_SEL {
TA_PERF_SEL_NULL                         = 0x00000000,
TA_PERF_SEL_sh_fifo_busy__GFX09          = 0x00000001,
TA_PERF_SEL_sh_fifo_cmd_busy__GFX09      = 0x00000002,
TA_PERF_SEL_sh_fifo_addr_busy__GFX09     = 0x00000003,
TA_PERF_SEL_sh_fifo_data_busy__GFX09     = 0x00000004,
TA_PERF_SEL_sh_fifo_data_sfifo_busy__GFX09 = 0x00000005,
TA_PERF_SEL_sh_fifo_data_tfifo_busy__GFX09 = 0x00000006,
TA_PERF_SEL_gradient_busy                = 0x00000007,
TA_PERF_SEL_gradient_fifo_busy           = 0x00000008,
TA_PERF_SEL_lod_busy                     = 0x00000009,
TA_PERF_SEL_lod_fifo_busy                = 0x0000000a,
TA_PERF_SEL_addresser_busy               = 0x0000000b,
TA_PERF_SEL_addresser_fifo_busy          = 0x0000000c,
TA_PERF_SEL_aligner_busy                 = 0x0000000d,
TA_PERF_SEL_write_path_busy              = 0x0000000e,
TA_PERF_SEL_ta_busy                      = 0x0000000f,
TA_PERF_SEL_sq_ta_cmd_cycles__GFX09      = 0x00000010,
TA_PERF_SEL_sp_ta_addr_cycles__GFX09     = 0x00000011,
TA_PERF_SEL_sp_ta_data_cycles__GFX09     = 0x00000012,
TA_PERF_SEL_ta_fa_data_state_cycles__GFX09 = 0x00000013,
TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles__GFX09 = 0x00000014,
TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles__GFX09 = 0x00000015,
TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles__GFX09 = 0x00000016,
TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles__GFX09 = 0x00000017,
TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles__GFX09 = 0x00000018,
TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles__GFX09 = 0x00000019,
TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles__GFX09 = 0x0000001a,
TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles__GFX09 = 0x0000001b,
TA_PERF_SEL_RESERVED_29                  = 0x0000001d,
TA_PERF_SEL_sh_fifo_addr_cycles__GFX09   = 0x0000001e,
TA_PERF_SEL_sh_fifo_data_cycles__GFX09   = 0x0000001f,
TA_PERF_SEL_total_wavefronts             = 0x00000020,
TA_PERF_SEL_gradient_cycles              = 0x00000021,
TA_PERF_SEL_walker_cycles                = 0x00000022,
TA_PERF_SEL_aligner_cycles               = 0x00000023,
TA_PERF_SEL_image_wavefronts             = 0x00000024,
TA_PERF_SEL_image_read_wavefronts        = 0x00000025,
TA_PERF_SEL_image_write_wavefronts       = 0x00000026,
TA_PERF_SEL_image_atomic_wavefronts      = 0x00000027,
TA_PERF_SEL_image_total_cycles__GFX09    = 0x00000028,
TA_PERF_SEL_RESERVED_41__GFX09           = 0x00000029,
TA_PERF_SEL_RESERVED_42__GFX09           = 0x0000002a,
TA_PERF_SEL_RESERVED_43                  = 0x0000002b,
TA_PERF_SEL_buffer_wavefronts            = 0x0000002c,
TA_PERF_SEL_buffer_read_wavefronts       = 0x0000002d,
TA_PERF_SEL_buffer_write_wavefronts      = 0x0000002e,
TA_PERF_SEL_buffer_atomic_wavefronts     = 0x0000002f,
TA_PERF_SEL_buffer_coalescable_wavefronts__GFX09 = 0x00000030,
TA_PERF_SEL_buffer_total_cycles          = 0x00000031,
TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles__GFX09 = 0x00000032,
TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles__GFX09 = 0x00000033,
TA_PERF_SEL_buffer_coalesced_read_cycles__GFX09 = 0x00000034,
TA_PERF_SEL_buffer_coalesced_write_cycles__GFX09 = 0x00000035,
TA_PERF_SEL_addr_stalled_by_tc_cycles    = 0x00000036,
TA_PERF_SEL_addr_stalled_by_td_cycles    = 0x00000037,
TA_PERF_SEL_data_stalled_by_tc_cycles__GFX09 = 0x00000038,
TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
TA_PERF_SEL_addresser_stalled_cycles     = 0x0000003a,
TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
TA_PERF_SEL_aniso_stalled_cycles         = 0x0000003c,
TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
TA_PERF_SEL_deriv_stalled_cycles         = 0x0000003e,
TA_PERF_SEL_aniso_gt1_cycle_quads        = 0x0000003f,
TA_PERF_SEL_color_1_cycle_pixels         = 0x00000040,
TA_PERF_SEL_color_2_cycle_pixels         = 0x00000041,
TA_PERF_SEL_color_3_cycle_pixels         = 0x00000042,
TA_PERF_SEL_color_4_cycle_pixels__GFX09  = 0x00000043,
TA_PERF_SEL_mip_1_cycle_pixels           = 0x00000044,
TA_PERF_SEL_mip_2_cycle_pixels           = 0x00000045,
TA_PERF_SEL_vol_1_cycle_pixels           = 0x00000046,
TA_PERF_SEL_vol_2_cycle_pixels           = 0x00000047,
TA_PERF_SEL_bilin_point_1_cycle_pixels   = 0x00000048,
TA_PERF_SEL_mipmap_lod_0_samples         = 0x00000049,
TA_PERF_SEL_mipmap_lod_1_samples         = 0x0000004a,
TA_PERF_SEL_mipmap_lod_2_samples         = 0x0000004b,
TA_PERF_SEL_mipmap_lod_3_samples         = 0x0000004c,
TA_PERF_SEL_mipmap_lod_4_samples         = 0x0000004d,
TA_PERF_SEL_mipmap_lod_5_samples         = 0x0000004e,
TA_PERF_SEL_mipmap_lod_6_samples         = 0x0000004f,
TA_PERF_SEL_mipmap_lod_7_samples         = 0x00000050,
TA_PERF_SEL_mipmap_lod_8_samples         = 0x00000051,
TA_PERF_SEL_mipmap_lod_9_samples         = 0x00000052,
TA_PERF_SEL_mipmap_lod_10_samples        = 0x00000053,
TA_PERF_SEL_mipmap_lod_11_samples        = 0x00000054,
TA_PERF_SEL_mipmap_lod_12_samples        = 0x00000055,
TA_PERF_SEL_mipmap_lod_13_samples        = 0x00000056,
TA_PERF_SEL_mipmap_lod_14_samples        = 0x00000057,
TA_PERF_SEL_mipmap_invalid_samples       = 0x00000058,
TA_PERF_SEL_aniso_1_cycle_quads          = 0x00000059,
TA_PERF_SEL_aniso_2_cycle_quads          = 0x0000005a,
TA_PERF_SEL_aniso_4_cycle_quads          = 0x0000005b,
TA_PERF_SEL_aniso_6_cycle_quads          = 0x0000005c,
TA_PERF_SEL_aniso_8_cycle_quads          = 0x0000005d,
TA_PERF_SEL_aniso_10_cycle_quads         = 0x0000005e,
TA_PERF_SEL_aniso_12_cycle_quads         = 0x0000005f,
TA_PERF_SEL_aniso_14_cycle_quads         = 0x00000060,
TA_PERF_SEL_aniso_16_cycle_quads         = 0x00000061,
TA_PERF_SEL_write_path_input_cycles      = 0x00000062,
TA_PERF_SEL_write_path_output_cycles     = 0x00000063,
TA_PERF_SEL_flat_wavefronts              = 0x00000064,
TA_PERF_SEL_flat_read_wavefronts         = 0x00000065,
TA_PERF_SEL_flat_write_wavefronts        = 0x00000066,
TA_PERF_SEL_flat_atomic_wavefronts       = 0x00000067,
TA_PERF_SEL_flat_coalesceable_wavefronts__GFX09 = 0x00000068,
TA_PERF_SEL_reg_sclk_vld                 = 0x00000069,
TA_PERF_SEL_local_cg_dyn_sclk_grp0_en    = 0x0000006a,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_en    = 0x0000006b,
TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c,
TA_PERF_SEL_local_cg_dyn_sclk_grp4_en    = 0x0000006d,
TA_PERF_SEL_local_cg_dyn_sclk_grp5_en    = 0x0000006e,
TA_PERF_SEL_xnack_on_phase0__GFX09       = 0x0000006f,
TA_PERF_SEL_xnack_on_phase1__GFX09       = 0x00000070,
TA_PERF_SEL_xnack_on_phase2__GFX09       = 0x00000071,
TA_PERF_SEL_xnack_on_phase3__GFX09       = 0x00000072,
TA_PERF_SEL_first_xnack_on_phase0__GFX09 = 0x00000073,
TA_PERF_SEL_first_xnack_on_phase1__GFX09 = 0x00000074,
TA_PERF_SEL_first_xnack_on_phase2__GFX09 = 0x00000075,
TA_PERF_SEL_first_xnack_on_phase3__GFX09 = 0x00000076,
} TA_PERFCOUNT_SEL;

typedef enum TA_TC_ADDR_MODES {
TA_TC_ADDR_MODE_DEFAULT                  = 0x00000000,
TA_TC_ADDR_MODE_COMP0                    = 0x00000001,
TA_TC_ADDR_MODE_COMP1                    = 0x00000002,
TA_TC_ADDR_MODE_COMP2                    = 0x00000003,
TA_TC_ADDR_MODE_COMP3                    = 0x00000004,
TA_TC_ADDR_MODE_UNALIGNED                = 0x00000005,
TA_TC_ADDR_MODE_BORDER_COLOR             = 0x00000006,
} TA_TC_ADDR_MODES;

typedef enum TCA_PERF_SEL {
TCA_PERF_SEL_NONE                        = 0x00000000,
TCA_PERF_SEL_CYCLE                       = 0x00000001,
TCA_PERF_SEL_BUSY                        = 0x00000002,
TCA_PERF_SEL_FORCED_HOLE_TCC0            = 0x00000003,
TCA_PERF_SEL_FORCED_HOLE_TCC1            = 0x00000004,
TCA_PERF_SEL_FORCED_HOLE_TCC2            = 0x00000005,
TCA_PERF_SEL_FORCED_HOLE_TCC3            = 0x00000006,
TCA_PERF_SEL_FORCED_HOLE_TCC4            = 0x00000007,
TCA_PERF_SEL_FORCED_HOLE_TCC5            = 0x00000008,
TCA_PERF_SEL_FORCED_HOLE_TCC6            = 0x00000009,
TCA_PERF_SEL_FORCED_HOLE_TCC7            = 0x0000000a,
TCA_PERF_SEL_REQ_TCC0                    = 0x0000000b,
TCA_PERF_SEL_REQ_TCC1                    = 0x0000000c,
TCA_PERF_SEL_REQ_TCC2                    = 0x0000000d,
TCA_PERF_SEL_REQ_TCC3                    = 0x0000000e,
TCA_PERF_SEL_REQ_TCC4                    = 0x0000000f,
TCA_PERF_SEL_REQ_TCC5                    = 0x00000010,
TCA_PERF_SEL_REQ_TCC6                    = 0x00000011,
TCA_PERF_SEL_REQ_TCC7                    = 0x00000012,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0    = 0x00000013,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1    = 0x00000014,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2    = 0x00000015,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3    = 0x00000016,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4    = 0x00000017,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5    = 0x00000018,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6    = 0x00000019,
TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7    = 0x0000001a,
TCA_PERF_SEL_CROSSBAR_STALL_TCC0         = 0x0000001b,
TCA_PERF_SEL_CROSSBAR_STALL_TCC1         = 0x0000001c,
TCA_PERF_SEL_CROSSBAR_STALL_TCC2         = 0x0000001d,
TCA_PERF_SEL_CROSSBAR_STALL_TCC3         = 0x0000001e,
TCA_PERF_SEL_CROSSBAR_STALL_TCC4         = 0x0000001f,
TCA_PERF_SEL_CROSSBAR_STALL_TCC5         = 0x00000020,
TCA_PERF_SEL_CROSSBAR_STALL_TCC6         = 0x00000021,
TCA_PERF_SEL_CROSSBAR_STALL_TCC7         = 0x00000022,
} TCA_PERF_SEL;

typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU                     = 0x00000000,
TCC_CACHE_POLICY_STREAM                  = 0x00000001,
} TCC_CACHE_POLICIES;

typedef enum TCC_PERF_SEL {
TCC_PERF_SEL_NONE                        = 0x00000000,
TCC_PERF_SEL_CYCLE                       = 0x00000001,
TCC_PERF_SEL_BUSY                        = 0x00000002,
TCC_PERF_SEL_REQ                         = 0x00000003,
TCC_PERF_SEL_STREAMING_REQ               = 0x00000004,
TCC_PERF_SEL_COMPRESSED_REQ              = 0x00000005,
TCC_PERF_SEL_COMPRESSED_0_REQ            = 0x00000006,
TCC_PERF_SEL_METADATA_REQ                = 0x00000008,
TCC_PERF_SEL_PROBE                       = 0x0000000c,
TCC_PERF_SEL_READ                        = 0x0000000f,
TCC_PERF_SEL_WRITE                       = 0x00000010,
TCC_PERF_SEL_ATOMIC                      = 0x00000011,
TCC_PERF_SEL_HIT                         = 0x00000014,
TCC_PERF_SEL_MISS                        = 0x00000016,
TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT        = 0x00000017,
TCC_PERF_SEL_FULLY_WRITTEN_HIT           = 0x00000018,
TCC_PERF_SEL_WRITEBACK                   = 0x00000019,
TCC_PERF_SEL_LATENCY_FIFO_FULL           = 0x0000001a,
TCC_PERF_SEL_SRC_FIFO_FULL               = 0x0000001b,
TCC_PERF_SEL_HOLE_FIFO_FULL              = 0x0000001c,
TCC_PERF_SEL_TAG_STALL                   = 0x00000032,
TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x00000033,
TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x00000034,
TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x00000035,
TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x00000036,
TCC_PERF_SEL_TAG_PROBE_STALL             = 0x00000037,
TCC_PERF_SEL_TAG_PROBE_FILTER_STALL      = 0x00000038,
TCC_PERF_SEL_READ_RETURN_TIMEOUT         = 0x0000003a,
TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT      = 0x0000003b,
TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE     = 0x0000003c,
TCC_PERF_SEL_BUBBLE                      = 0x0000003d,
TCC_PERF_SEL_RETURN_ACK                  = 0x0000003e,
TCC_PERF_SEL_RETURN_DATA                 = 0x0000003f,
TCC_PERF_SEL_RETURN_HOLE                 = 0x00000040,
TCC_PERF_SEL_RETURN_ACK_HOLE             = 0x00000041,
TCC_PERF_SEL_IB_REQ                      = 0x00000042,
TCC_PERF_SEL_IB_STALL                    = 0x00000043,
TCC_PERF_SEL_IB_TAG_STALL                = 0x00000044,
TCC_PERF_SEL_IB_MDC_STALL                = 0x00000045,
TCC_PERF_SEL_TCA_LEVEL                   = 0x00000046,
TCC_PERF_SEL_HOLE_LEVEL                  = 0x00000047,
TCC_PERF_SEL_NORMAL_WRITEBACK            = 0x0000004a,
TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK     = 0x0000004b,
TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK     = 0x0000004c,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK  = 0x0000004d,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK  = 0x0000004e,
TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK      = 0x0000004f,
TCC_PERF_SEL_NORMAL_EVICT                = 0x00000050,
TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT         = 0x00000051,
TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT        = 0x00000052,
TCC_PERF_SEL_TC_OP_WBINVL2_EVICT         = 0x00000053,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT      = 0x00000054,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT      = 0x00000055,
TCC_PERF_SEL_ALL_TC_OP_INV_EVICT         = 0x00000056,
TCC_PERF_SEL_PROBE_EVICT                 = 0x00000057,
TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE         = 0x00000058,
TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE        = 0x00000059,
TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE         = 0x0000005a,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE      = 0x0000005b,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE      = 0x0000005c,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE   = 0x0000005d,
TCC_PERF_SEL_TC_OP_WBL2_NC_START         = 0x0000005e,
TCC_PERF_SEL_TC_OP_INVL2_NC_START        = 0x0000005f,
TCC_PERF_SEL_TC_OP_WBINVL2_START         = 0x00000060,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_START      = 0x00000061,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_START      = 0x00000062,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START   = 0x00000063,
TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH        = 0x00000064,
TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH       = 0x00000065,
TCC_PERF_SEL_TC_OP_WBINVL2_FINISH        = 0x00000066,
TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH     = 0x00000067,
TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH     = 0x00000068,
TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH  = 0x00000069,
TCC_PERF_SEL_MDC_REQ                     = 0x0000006b,
TCC_PERF_SEL_MDC_LEVEL                   = 0x0000006c,
TCC_PERF_SEL_MDC_TAG_HIT                 = 0x0000006d,
TCC_PERF_SEL_MDC_SECTOR_HIT              = 0x0000006e,
TCC_PERF_SEL_MDC_SECTOR_MISS             = 0x0000006f,
TCC_PERF_SEL_MDC_TAG_STALL               = 0x00000070,
TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x00000071,
TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x00000072,
TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x00000073,
TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000074,
TCC_PERF_SEL_PROBE_FILTER_DISABLED       = 0x00000075,
TCC_PERF_SEL_CLIENT0_REQ                 = 0x00000080,
TCC_PERF_SEL_CLIENT1_REQ                 = 0x00000081,
TCC_PERF_SEL_CLIENT2_REQ                 = 0x00000082,
TCC_PERF_SEL_CLIENT3_REQ                 = 0x00000083,
TCC_PERF_SEL_CLIENT4_REQ                 = 0x00000084,
TCC_PERF_SEL_CLIENT5_REQ                 = 0x00000085,
TCC_PERF_SEL_CLIENT6_REQ                 = 0x00000086,
TCC_PERF_SEL_CLIENT7_REQ                 = 0x00000087,
TCC_PERF_SEL_CLIENT8_REQ                 = 0x00000088,
TCC_PERF_SEL_CLIENT9_REQ                 = 0x00000089,
TCC_PERF_SEL_CLIENT10_REQ                = 0x0000008a,
TCC_PERF_SEL_CLIENT11_REQ                = 0x0000008b,
TCC_PERF_SEL_CLIENT12_REQ                = 0x0000008c,
TCC_PERF_SEL_CLIENT13_REQ                = 0x0000008d,
TCC_PERF_SEL_CLIENT14_REQ                = 0x0000008e,
TCC_PERF_SEL_CLIENT15_REQ                = 0x0000008f,
TCC_PERF_SEL_CLIENT16_REQ                = 0x00000090,
TCC_PERF_SEL_CLIENT17_REQ                = 0x00000091,
TCC_PERF_SEL_CLIENT18_REQ                = 0x00000092,
TCC_PERF_SEL_CLIENT19_REQ                = 0x00000093,
TCC_PERF_SEL_CLIENT20_REQ                = 0x00000094,
TCC_PERF_SEL_CLIENT21_REQ                = 0x00000095,
TCC_PERF_SEL_CLIENT22_REQ                = 0x00000096,
TCC_PERF_SEL_CLIENT23_REQ                = 0x00000097,
TCC_PERF_SEL_CLIENT24_REQ                = 0x00000098,
TCC_PERF_SEL_CLIENT25_REQ                = 0x00000099,
TCC_PERF_SEL_CLIENT26_REQ                = 0x0000009a,
TCC_PERF_SEL_CLIENT27_REQ                = 0x0000009b,
TCC_PERF_SEL_CLIENT28_REQ                = 0x0000009c,
TCC_PERF_SEL_CLIENT29_REQ                = 0x0000009d,
TCC_PERF_SEL_CLIENT30_REQ                = 0x0000009e,
TCC_PERF_SEL_CLIENT31_REQ                = 0x0000009f,
TCC_PERF_SEL_CLIENT32_REQ                = 0x000000a0,
TCC_PERF_SEL_CLIENT33_REQ                = 0x000000a1,
TCC_PERF_SEL_CLIENT34_REQ                = 0x000000a2,
TCC_PERF_SEL_CLIENT35_REQ                = 0x000000a3,
TCC_PERF_SEL_CLIENT36_REQ                = 0x000000a4,
TCC_PERF_SEL_CLIENT37_REQ                = 0x000000a5,
TCC_PERF_SEL_CLIENT38_REQ                = 0x000000a6,
TCC_PERF_SEL_CLIENT39_REQ                = 0x000000a7,
TCC_PERF_SEL_CLIENT40_REQ                = 0x000000a8,
TCC_PERF_SEL_CLIENT41_REQ                = 0x000000a9,
TCC_PERF_SEL_CLIENT42_REQ                = 0x000000aa,
TCC_PERF_SEL_CLIENT43_REQ                = 0x000000ab,
TCC_PERF_SEL_CLIENT44_REQ                = 0x000000ac,
TCC_PERF_SEL_CLIENT45_REQ                = 0x000000ad,
TCC_PERF_SEL_CLIENT46_REQ                = 0x000000ae,
TCC_PERF_SEL_CLIENT47_REQ                = 0x000000af,
TCC_PERF_SEL_CLIENT48_REQ                = 0x000000b0,
TCC_PERF_SEL_CLIENT49_REQ                = 0x000000b1,
TCC_PERF_SEL_CLIENT50_REQ                = 0x000000b2,
TCC_PERF_SEL_CLIENT51_REQ                = 0x000000b3,
TCC_PERF_SEL_CLIENT52_REQ                = 0x000000b4,
TCC_PERF_SEL_CLIENT53_REQ                = 0x000000b5,
TCC_PERF_SEL_CLIENT54_REQ                = 0x000000b6,
TCC_PERF_SEL_CLIENT55_REQ                = 0x000000b7,
TCC_PERF_SEL_CLIENT56_REQ                = 0x000000b8,
TCC_PERF_SEL_CLIENT57_REQ                = 0x000000b9,
TCC_PERF_SEL_CLIENT58_REQ                = 0x000000ba,
TCC_PERF_SEL_CLIENT59_REQ                = 0x000000bb,
TCC_PERF_SEL_CLIENT60_REQ                = 0x000000bc,
TCC_PERF_SEL_CLIENT61_REQ                = 0x000000bd,
TCC_PERF_SEL_CLIENT62_REQ                = 0x000000be,
TCC_PERF_SEL_CLIENT63_REQ                = 0x000000bf,
TCC_PERF_SEL_CLIENT64_REQ                = 0x000000c0,
TCC_PERF_SEL_CLIENT65_REQ                = 0x000000c1,
TCC_PERF_SEL_CLIENT66_REQ                = 0x000000c2,
TCC_PERF_SEL_CLIENT67_REQ                = 0x000000c3,
TCC_PERF_SEL_CLIENT68_REQ                = 0x000000c4,
TCC_PERF_SEL_CLIENT69_REQ                = 0x000000c5,
TCC_PERF_SEL_CLIENT70_REQ                = 0x000000c6,
TCC_PERF_SEL_CLIENT71_REQ                = 0x000000c7,
TCC_PERF_SEL_CLIENT72_REQ                = 0x000000c8,
TCC_PERF_SEL_CLIENT73_REQ                = 0x000000c9,
TCC_PERF_SEL_CLIENT74_REQ                = 0x000000ca,
TCC_PERF_SEL_CLIENT75_REQ                = 0x000000cb,
TCC_PERF_SEL_CLIENT76_REQ                = 0x000000cc,
TCC_PERF_SEL_CLIENT77_REQ                = 0x000000cd,
TCC_PERF_SEL_CLIENT78_REQ                = 0x000000ce,
TCC_PERF_SEL_CLIENT79_REQ                = 0x000000cf,
TCC_PERF_SEL_CLIENT80_REQ                = 0x000000d0,
TCC_PERF_SEL_CLIENT81_REQ                = 0x000000d1,
TCC_PERF_SEL_CLIENT82_REQ                = 0x000000d2,
TCC_PERF_SEL_CLIENT83_REQ                = 0x000000d3,
TCC_PERF_SEL_CLIENT84_REQ                = 0x000000d4,
TCC_PERF_SEL_CLIENT85_REQ                = 0x000000d5,
TCC_PERF_SEL_CLIENT86_REQ                = 0x000000d6,
TCC_PERF_SEL_CLIENT87_REQ                = 0x000000d7,
TCC_PERF_SEL_CLIENT88_REQ                = 0x000000d8,
TCC_PERF_SEL_CLIENT89_REQ                = 0x000000d9,
TCC_PERF_SEL_CLIENT90_REQ                = 0x000000da,
TCC_PERF_SEL_CLIENT91_REQ                = 0x000000db,
TCC_PERF_SEL_CLIENT92_REQ                = 0x000000dc,
TCC_PERF_SEL_CLIENT93_REQ                = 0x000000dd,
TCC_PERF_SEL_CLIENT94_REQ                = 0x000000de,
TCC_PERF_SEL_CLIENT95_REQ                = 0x000000df,
TCC_PERF_SEL_CLIENT96_REQ                = 0x000000e0,
TCC_PERF_SEL_CLIENT97_REQ                = 0x000000e1,
TCC_PERF_SEL_CLIENT98_REQ                = 0x000000e2,
TCC_PERF_SEL_CLIENT99_REQ                = 0x000000e3,
TCC_PERF_SEL_CLIENT100_REQ               = 0x000000e4,
TCC_PERF_SEL_CLIENT101_REQ               = 0x000000e5,
TCC_PERF_SEL_CLIENT102_REQ               = 0x000000e6,
TCC_PERF_SEL_CLIENT103_REQ               = 0x000000e7,
TCC_PERF_SEL_CLIENT104_REQ               = 0x000000e8,
TCC_PERF_SEL_CLIENT105_REQ               = 0x000000e9,
TCC_PERF_SEL_CLIENT106_REQ               = 0x000000ea,
TCC_PERF_SEL_CLIENT107_REQ               = 0x000000eb,
TCC_PERF_SEL_CLIENT108_REQ               = 0x000000ec,
TCC_PERF_SEL_CLIENT109_REQ               = 0x000000ed,
TCC_PERF_SEL_CLIENT110_REQ               = 0x000000ee,
TCC_PERF_SEL_CLIENT111_REQ               = 0x000000ef,
TCC_PERF_SEL_CLIENT112_REQ               = 0x000000f0,
TCC_PERF_SEL_CLIENT113_REQ               = 0x000000f1,
TCC_PERF_SEL_CLIENT114_REQ               = 0x000000f2,
TCC_PERF_SEL_CLIENT115_REQ               = 0x000000f3,
TCC_PERF_SEL_CLIENT116_REQ               = 0x000000f4,
TCC_PERF_SEL_CLIENT117_REQ               = 0x000000f5,
TCC_PERF_SEL_CLIENT118_REQ               = 0x000000f6,
TCC_PERF_SEL_CLIENT119_REQ               = 0x000000f7,
TCC_PERF_SEL_CLIENT120_REQ               = 0x000000f8,
TCC_PERF_SEL_CLIENT121_REQ               = 0x000000f9,
TCC_PERF_SEL_CLIENT122_REQ               = 0x000000fa,
TCC_PERF_SEL_CLIENT123_REQ               = 0x000000fb,
TCC_PERF_SEL_CLIENT124_REQ               = 0x000000fc,
TCC_PERF_SEL_CLIENT125_REQ               = 0x000000fd,
TCC_PERF_SEL_CLIENT126_REQ               = 0x000000fe,
TCC_PERF_SEL_CLIENT127_REQ               = 0x000000ff,
} TCC_PERF_SEL;

typedef enum TCP_CACHE_POLICIES {
TCP_CACHE_POLICY_MISS_LRU                = 0x00000000,
TCP_CACHE_POLICY_MISS_EVICT              = 0x00000001,
TCP_CACHE_POLICY_HIT_LRU                 = 0x00000002,
TCP_CACHE_POLICY_HIT_EVICT               = 0x00000003,
} TCP_CACHE_POLICIES;

typedef enum TCP_CACHE_STORE_POLICIES {
TCP_CACHE_STORE_POLICY_WT_LRU            = 0x00000000,
TCP_CACHE_STORE_POLICY_WT_EVICT          = 0x00000001,
} TCP_CACHE_STORE_POLICIES;

typedef enum TCP_DSM_DATA_SEL {
TCP_DSM_DISABLE                          = 0x00000000,
TCP_DSM_SEL0                             = 0x00000001,
TCP_DSM_SEL1                             = 0x00000002,
TCP_DSM_SEL_BOTH                         = 0x00000003,
} TCP_DSM_DATA_SEL;

typedef enum TCP_DSM_INJECT_SEL {
} TCP_DSM_INJECT_SEL;

typedef enum TCP_DSM_SINGLE_WRITE {
TCP_DSM_SINGLE_WRITE_EN                  = 0x00000001,
} TCP_DSM_SINGLE_WRITE;

typedef enum TCP_PERFCOUNT_SELECT {
TCP_PERF_SEL_GATE_EN1                    = 0x00000000,
TCP_PERF_SEL_GATE_EN2                    = 0x00000001,
TCP_PERF_SEL_CORE_REG_SCLK_VLD__GFX09    = 0x00000002,
TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES__GFX09 = 0x00000003,
TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES__GFX09 = 0x00000004,
TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES__GFX09 = 0x00000005,
TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES__GFX09 = 0x00000006,
TCP_PERF_SEL_TD_TCP_STALL_CYCLES__GFX09  = 0x00000007,
TCP_PERF_SEL_TCR_TCP_STALL_CYCLES__GFX09 = 0x00000008,
TCP_PERF_SEL_LOD_STALL_CYCLES__GFX09     = 0x0000000a,
TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES__GFX09 = 0x0000000b,
TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES__GFX09 = 0x0000000c,
TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES__GFX09 = 0x0000000d,
TCP_PERF_SEL_ALLOC_STALL_CYCLES__GFX09   = 0x0000000e,
TCP_PERF_SEL_UNORDERED_MTYPE_STALL__GFX09 = 0x0000000f,
TCP_PERF_SEL_LFIFO_STALL_CYCLES__GFX09   = 0x00000010,
TCP_PERF_SEL_RFIFO_STALL_CYCLES__GFX09   = 0x00000011,
TCP_PERF_SEL_TCR_RDRET_STALL__GFX09      = 0x00000012,
TCP_PERF_SEL_WRITE_CONFLICT_STALL__GFX09 = 0x00000013,
TCP_PERF_SEL_HOLE_READ_STALL__GFX09      = 0x00000014,
TCP_PERF_SEL_READCONFLICT_STALL_CYCLES__GFX09 = 0x00000015,
TCP_PERF_SEL_PENDING_STALL_CYCLES__GFX09 = 0x00000016,
TCP_PERF_SEL_READFIFO_STALL_CYCLES__GFX09 = 0x00000017,
TCP_PERF_SEL_POWER_STALL__GFX09          = 0x00000018,
TCP_PERF_SEL_TC_TA_XNACK_STALL__GFX09    = 0x0000001a,
TCP_PERF_SEL_TA_TCP_STATE_READ__GFX09    = 0x0000001b,
TCP_PERF_SEL_VOLATILE__GFX09             = 0x0000001c,
TCP_PERF_SEL_TOTAL_ACCESSES__GFX09       = 0x0000001d,
TCP_PERF_SEL_TOTAL_READ__GFX09           = 0x0000001e,
TCP_PERF_SEL_TOTAL_NON_READ__GFX09       = 0x0000001f,
TCP_PERF_SEL_TOTAL_WRITE__GFX09          = 0x00000020,
TCP_PERF_SEL_TOTAL_HIT_LRU_READ__GFX09   = 0x00000021,
TCP_PERF_SEL_TOTAL_MISS_LRU_READ__GFX09  = 0x00000022,
TCP_PERF_SEL_TOTAL_MISS_EVICT_READ__GFX09 = 0x00000023,
TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE__GFX09 = 0x00000024,
TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE__GFX09 = 0x00000025,
TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET__GFX09 = 0x00000026,
TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET__GFX09 = 0x00000027,
TCP_PERF_SEL_TOTAL_WBINVL1__GFX09        = 0x00000028,
TCP_PERF_SEL_TOTAL_WBINVL1_VOL__GFX09    = 0x00000029,
TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL__GFX09 = 0x0000002a,
TCP_PERF_SEL_CP_TCP_INVALIDATE__GFX09    = 0x0000002b,
TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL__GFX09 = 0x0000002c,
TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES__GFX09 = 0x0000002d,
TCP_PERF_SEL_SHOOTDOWN__GFX09            = 0x0000002e,
TCP_PERF_SEL_TAGRAM0_REQ__GFX09          = 0x0000003d,
TCP_PERF_SEL_TAGRAM1_REQ__GFX09          = 0x0000003e,
TCP_PERF_SEL_TAGRAM2_REQ__GFX09          = 0x0000003f,
TCP_PERF_SEL_TAGRAM3_REQ__GFX09          = 0x00000040,
TCP_PERF_SEL_TCP_LATENCY__GFX09          = 0x00000041,
TCP_PERF_SEL_TCC_READ_REQ_LATENCY__GFX09 = 0x00000042,
TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY__GFX09 = 0x00000043,
TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY__GFX09 = 0x00000044,
TCP_PERF_SEL_TCC_READ_REQ__GFX09         = 0x00000045,
TCP_PERF_SEL_TCC_WRITE_REQ__GFX09        = 0x00000046,
TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ__GFX09 = 0x00000047,
TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ__GFX09 = 0x00000048,
TCP_PERF_SEL_TCC_LRU_REQ__GFX09          = 0x00000049,
TCP_PERF_SEL_TCC_STREAM_REQ__GFX09       = 0x0000004a,
TCP_PERF_SEL_TCC_NC_READ_REQ__GFX09      = 0x0000004b,
TCP_PERF_SEL_TCC_NC_WRITE_REQ__GFX09     = 0x0000004c,
TCP_PERF_SEL_TCC_NC_ATOMIC_REQ__GFX09    = 0x0000004d,
TCP_PERF_SEL_TCC_UC_READ_REQ__GFX09      = 0x0000004e,
TCP_PERF_SEL_TCC_UC_WRITE_REQ__GFX09     = 0x0000004f,
TCP_PERF_SEL_TCC_UC_ATOMIC_REQ__GFX09    = 0x00000050,
TCP_PERF_SEL_TCC_CC_READ_REQ__GFX09      = 0x00000051,
TCP_PERF_SEL_TCC_CC_WRITE_REQ__GFX09     = 0x00000052,
TCP_PERF_SEL_TCC_CC_ATOMIC_REQ__GFX09    = 0x00000053,
TCP_PERF_SEL_TCC_DCC_REQ__GFX09          = 0x00000054,
} TCP_PERFCOUNT_SELECT;

typedef enum TCP_WATCH_MODES {
TCP_WATCH_MODE_READ                      = 0x00000000,
TCP_WATCH_MODE_NONREAD                   = 0x00000001,
TCP_WATCH_MODE_ATOMIC                    = 0x00000002,
TCP_WATCH_MODE_ALL                       = 0x00000003,
} TCP_WATCH_MODES;

typedef enum TC_EA_CID {
} TC_EA_CID;

typedef enum TC_MICRO_TILE_MODE {
} TC_MICRO_TILE_MODE;

typedef enum TC_NACKS {
TC_NACK_NO_FAULT                         = 0x00000000,
TC_NACK_PAGE_FAULT                       = 0x00000001,
TC_NACK_PROTECTION_FAULT                 = 0x00000002,
TC_NACK_DATA_ERROR                       = 0x00000003,
} TC_NACKS;

typedef enum TC_OP {
TC_OP_READ                               = 0x00000000,
TC_OP_ATOMIC_FCMPSWAP_RTN_32             = 0x00000001,
TC_OP_ATOMIC_FMIN_RTN_32                 = 0x00000002,
TC_OP_ATOMIC_FMAX_RTN_32                 = 0x00000003,
TC_OP_RESERVED_FOP_RTN_32_0              = 0x00000004,
TC_OP_RESERVED_FOP_RTN_32_1              = 0x00000005,
TC_OP_RESERVED_FOP_RTN_32_2              = 0x00000006,
TC_OP_ATOMIC_SWAP_RTN_32                 = 0x00000007,
TC_OP_ATOMIC_CMPSWAP_RTN_32              = 0x00000008,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32    = 0x0000000a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32    = 0x0000000b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
TC_OP_ATOMIC_ADD_RTN_32                  = 0x0000000f,
TC_OP_ATOMIC_SUB_RTN_32                  = 0x00000010,
TC_OP_ATOMIC_SMIN_RTN_32                 = 0x00000011,
TC_OP_ATOMIC_UMIN_RTN_32                 = 0x00000012,
TC_OP_ATOMIC_SMAX_RTN_32                 = 0x00000013,
TC_OP_ATOMIC_UMAX_RTN_32                 = 0x00000014,
TC_OP_ATOMIC_AND_RTN_32                  = 0x00000015,
TC_OP_ATOMIC_OR_RTN_32                   = 0x00000016,
TC_OP_ATOMIC_XOR_RTN_32                  = 0x00000017,
TC_OP_ATOMIC_INC_RTN_32                  = 0x00000018,
TC_OP_ATOMIC_DEC_RTN_32                  = 0x00000019,
TC_OP_WBINVL1_VOL                        = 0x0000001a,
TC_OP_WBINVL1_SD                         = 0x0000001b,
TC_OP_RESERVED_NON_FLOAT_RTN_32_0        = 0x0000001c,
TC_OP_RESERVED_NON_FLOAT_RTN_32_1        = 0x0000001d,
TC_OP_RESERVED_NON_FLOAT_RTN_32_2        = 0x0000001e,
TC_OP_RESERVED_NON_FLOAT_RTN_32_3        = 0x0000001f,
TC_OP_WRITE                              = 0x00000020,
TC_OP_ATOMIC_FCMPSWAP_RTN_64             = 0x00000021,
TC_OP_ATOMIC_FMIN_RTN_64                 = 0x00000022,
TC_OP_ATOMIC_FMAX_RTN_64                 = 0x00000023,
TC_OP_RESERVED_FOP_RTN_64_0              = 0x00000024,
TC_OP_RESERVED_FOP_RTN_64_1              = 0x00000025,
TC_OP_RESERVED_FOP_RTN_64_2              = 0x00000026,
TC_OP_ATOMIC_SWAP_RTN_64                 = 0x00000027,
TC_OP_ATOMIC_CMPSWAP_RTN_64              = 0x00000028,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64    = 0x0000002a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64    = 0x0000002b,
TC_OP_WBINVL2_SD                         = 0x0000002c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
TC_OP_ATOMIC_ADD_RTN_64                  = 0x0000002f,
TC_OP_ATOMIC_SUB_RTN_64                  = 0x00000030,
TC_OP_ATOMIC_SMIN_RTN_64                 = 0x00000031,
TC_OP_ATOMIC_UMIN_RTN_64                 = 0x00000032,
TC_OP_ATOMIC_SMAX_RTN_64                 = 0x00000033,
TC_OP_ATOMIC_UMAX_RTN_64                 = 0x00000034,
TC_OP_ATOMIC_AND_RTN_64                  = 0x00000035,
TC_OP_ATOMIC_OR_RTN_64                   = 0x00000036,
TC_OP_ATOMIC_XOR_RTN_64                  = 0x00000037,
TC_OP_ATOMIC_INC_RTN_64                  = 0x00000038,
TC_OP_ATOMIC_DEC_RTN_64                  = 0x00000039,
TC_OP_WBL2_NC                            = 0x0000003a,
TC_OP_RESERVED_NON_FLOAT_RTN_64_1        = 0x0000003c,
TC_OP_RESERVED_NON_FLOAT_RTN_64_2        = 0x0000003d,
TC_OP_RESERVED_NON_FLOAT_RTN_64_3        = 0x0000003e,
TC_OP_RESERVED_NON_FLOAT_RTN_64_4        = 0x0000003f,
TC_OP_WBINVL1                            = 0x00000040,
TC_OP_ATOMIC_FCMPSWAP_32                 = 0x00000041,
TC_OP_ATOMIC_FMIN_32                     = 0x00000042,
TC_OP_ATOMIC_FMAX_32                     = 0x00000043,
TC_OP_RESERVED_FOP_32_0                  = 0x00000044,
TC_OP_RESERVED_FOP_32_1                  = 0x00000045,
TC_OP_RESERVED_FOP_32_2                  = 0x00000046,
TC_OP_ATOMIC_SWAP_32                     = 0x00000047,
TC_OP_ATOMIC_CMPSWAP_32                  = 0x00000048,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32    = 0x00000049,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32        = 0x0000004a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32        = 0x0000004b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1     = 0x0000004d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2     = 0x0000004e,
TC_OP_ATOMIC_ADD_32                      = 0x0000004f,
TC_OP_ATOMIC_SUB_32                      = 0x00000050,
TC_OP_ATOMIC_SMIN_32                     = 0x00000051,
TC_OP_ATOMIC_UMIN_32                     = 0x00000052,
TC_OP_ATOMIC_SMAX_32                     = 0x00000053,
TC_OP_ATOMIC_UMAX_32                     = 0x00000054,
TC_OP_ATOMIC_AND_32                      = 0x00000055,
TC_OP_ATOMIC_OR_32                       = 0x00000056,
TC_OP_ATOMIC_XOR_32                      = 0x00000057,
TC_OP_ATOMIC_INC_32                      = 0x00000058,
TC_OP_ATOMIC_DEC_32                      = 0x00000059,
TC_OP_INVL2_NC                           = 0x0000005a,
TC_OP_RESERVED_NON_FLOAT_32_1            = 0x0000005c,
TC_OP_RESERVED_NON_FLOAT_32_2            = 0x0000005d,
TC_OP_RESERVED_NON_FLOAT_32_3            = 0x0000005e,
TC_OP_RESERVED_NON_FLOAT_32_4            = 0x0000005f,
TC_OP_WBINVL2                            = 0x00000060,
TC_OP_ATOMIC_FCMPSWAP_64                 = 0x00000061,
TC_OP_ATOMIC_FMIN_64                     = 0x00000062,
TC_OP_ATOMIC_FMAX_64                     = 0x00000063,
TC_OP_RESERVED_FOP_64_0                  = 0x00000064,
TC_OP_RESERVED_FOP_64_1                  = 0x00000065,
TC_OP_RESERVED_FOP_64_2                  = 0x00000066,
TC_OP_ATOMIC_SWAP_64                     = 0x00000067,
TC_OP_ATOMIC_CMPSWAP_64                  = 0x00000068,
TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64    = 0x00000069,
TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64        = 0x0000006a,
TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64        = 0x0000006b,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0     = 0x0000006c,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1     = 0x0000006d,
TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2     = 0x0000006e,
TC_OP_ATOMIC_ADD_64                      = 0x0000006f,
TC_OP_ATOMIC_SUB_64                      = 0x00000070,
TC_OP_ATOMIC_SMIN_64                     = 0x00000071,
TC_OP_ATOMIC_UMIN_64                     = 0x00000072,
TC_OP_ATOMIC_SMAX_64                     = 0x00000073,
TC_OP_ATOMIC_UMAX_64                     = 0x00000074,
TC_OP_ATOMIC_AND_64                      = 0x00000075,
TC_OP_ATOMIC_OR_64                       = 0x00000076,
TC_OP_ATOMIC_XOR_64                      = 0x00000077,
TC_OP_ATOMIC_INC_64                      = 0x00000078,
TC_OP_ATOMIC_DEC_64                      = 0x00000079,
TC_OP_WBINVL2_NC                         = 0x0000007a,
TC_OP_RESERVED_NON_FLOAT_64_1            = 0x0000007c,
TC_OP_RESERVED_NON_FLOAT_64_2            = 0x0000007d,
TC_OP_RESERVED_NON_FLOAT_64_3            = 0x0000007e,
TC_OP_RESERVED_NON_FLOAT_64_4            = 0x0000007f,
} TC_OP;

typedef enum TC_OP_MASKS {
TC_OP_MASK_FLUSH_DENROM                  = 0x00000008,
TC_OP_MASK_64                            = 0x00000020,
TC_OP_MASK_NO_RTN                        = 0x00000040,
} TC_OP_MASKS;

typedef enum TD_PERFCOUNT_SEL {
TD_PERF_SEL_none                         = 0x00000000,
TD_PERF_SEL_td_busy                      = 0x00000001,
TD_PERF_SEL_input_busy                   = 0x00000002,
TD_PERF_SEL_output_busy__GFX09           = 0x00000003,
TD_PERF_SEL_lerp_busy__GFX09             = 0x00000004,
TD_PERF_SEL_reg_sclk_vld__GFX09          = 0x00000005,
TD_PERF_SEL_local_cg_dyn_sclk_grp0_en__GFX09 = 0x00000006,
TD_PERF_SEL_local_cg_dyn_sclk_grp1_en__GFX09 = 0x00000007,
TD_PERF_SEL_local_cg_dyn_sclk_grp4_en__GFX09 = 0x00000008,
TD_PERF_SEL_local_cg_dyn_sclk_grp5_en__GFX09 = 0x00000009,
TD_PERF_SEL_tc_td_fifo_full__GFX09       = 0x0000000a,
TD_PERF_SEL_output_fifo_full__GFX09      = 0x0000000b,
TD_PERF_SEL_RESERVED_14__GFX09           = 0x0000000e,
TD_PERF_SEL_tc_stall__GFX09              = 0x0000000f,
TD_PERF_SEL_pc_stall__GFX09              = 0x00000010,
TD_PERF_SEL_gds_stall__GFX09             = 0x00000011,
TD_PERF_SEL_RESERVED_18__GFX09           = 0x00000012,
TD_PERF_SEL_RESERVED_19__GFX09           = 0x00000013,
TD_PERF_SEL_gather4_wavefront__GFX09     = 0x00000014,
TD_PERF_SEL_sample_c_wavefront__GFX09    = 0x00000018,
TD_PERF_SEL_load_wavefront__GFX09        = 0x00000019,
TD_PERF_SEL_atomic_wavefront__GFX09      = 0x0000001a,
TD_PERF_SEL_store_wavefront__GFX09       = 0x0000001b,
TD_PERF_SEL_ldfptr_wavefront             = 0x0000001c,
TD_PERF_SEL_d16_en_wavefront__GFX09      = 0x0000001d,
TD_PERF_SEL_bypass_filter_wavefront__GFX09 = 0x0000001e,
TD_PERF_SEL_min_max_filter_wavefront__GFX09 = 0x0000001f,
TD_PERF_SEL_coalescable_wavefront__GFX09 = 0x00000020,
TD_PERF_SEL_coalesced_phase__GFX09       = 0x00000021,
TD_PERF_SEL_four_phase_wavefront__GFX09  = 0x00000022,
TD_PERF_SEL_eight_phase_wavefront__GFX09 = 0x00000023,
TD_PERF_SEL_sixteen_phase_wavefront__GFX09 = 0x00000024,
TD_PERF_SEL_four_phase_forward_wavefront__GFX09 = 0x00000025,
TD_PERF_SEL_write_ack_wavefront__GFX09   = 0x00000026,
TD_PERF_SEL_RESERVED_39__GFX09           = 0x00000027,
TD_PERF_SEL_user_defined_border__GFX09   = 0x00000028,
TD_PERF_SEL_white_border__GFX09          = 0x00000029,
TD_PERF_SEL_opaque_black_border__GFX09   = 0x0000002a,
TD_PERF_SEL_RESERVED_43__GFX09           = 0x0000002b,
TD_PERF_SEL_RESERVED_44__GFX09           = 0x0000002c,
TD_PERF_SEL_nack__GFX09                  = 0x0000002d,
TD_PERF_SEL_td_sp_traffic__GFX09         = 0x0000002e,
TD_PERF_SEL_consume_gds_traffic__GFX09   = 0x0000002f,
TD_PERF_SEL_addresscmd_poison__GFX09     = 0x00000030,
TD_PERF_SEL_data_poison__GFX09           = 0x00000031,
TD_PERF_SEL_start_cycle_0__GFX09         = 0x00000032,
TD_PERF_SEL_start_cycle_1__GFX09         = 0x00000033,
TD_PERF_SEL_start_cycle_2__GFX09         = 0x00000034,
TD_PERF_SEL_start_cycle_3__GFX09         = 0x00000035,
TD_PERF_SEL_null_cycle_output__GFX09     = 0x00000036,
TD_PERF_SEL_d16_data_packed__GFX09       = 0x00000037,
TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt__GFX09 = 0x00000038,
} TD_PERFCOUNT_SEL;

typedef enum TEX_BC_SWIZZLE {
TEX_BC_Swizzle_XYZW                      = 0x00000000,
TEX_BC_Swizzle_XWYZ                      = 0x00000001,
TEX_BC_Swizzle_WZYX                      = 0x00000002,
TEX_BC_Swizzle_WXYZ                      = 0x00000003,
TEX_BC_Swizzle_ZYXW                      = 0x00000004,
TEX_BC_Swizzle_YXWZ                      = 0x00000005,
} TEX_BC_SWIZZLE;

typedef enum TEX_BORDER_COLOR_TYPE {
TEX_BorderColor_TransparentBlack         = 0x00000000,
TEX_BorderColor_OpaqueBlack              = 0x00000001,
TEX_BorderColor_OpaqueWhite              = 0x00000002,
TEX_BorderColor_Register                 = 0x00000003,
} TEX_BORDER_COLOR_TYPE;

typedef enum TEX_CHROMA_KEY {
TEX_ChromaKey_Disabled                   = 0x00000000,
TEX_ChromaKey_Kill                       = 0x00000001,
TEX_ChromaKey_Blend                      = 0x00000002,
TEX_ChromaKey_RESERVED_3                 = 0x00000003,
} TEX_CHROMA_KEY;

typedef enum TEX_CLAMP {
TEX_Clamp_Repeat                         = 0x00000000,
TEX_Clamp_Mirror                         = 0x00000001,
TEX_Clamp_ClampToLast                    = 0x00000002,
TEX_Clamp_MirrorOnceToLast               = 0x00000003,
TEX_Clamp_ClampHalfToBorder              = 0x00000004,
TEX_Clamp_MirrorOnceHalfToBorder         = 0x00000005,
TEX_Clamp_ClampToBorder                  = 0x00000006,
TEX_Clamp_MirrorOnceToBorder             = 0x00000007,
} TEX_CLAMP;

typedef enum TEX_COORD_TYPE {
TEX_CoordType_Unnormalized               = 0x00000000,
TEX_CoordType_Normalized                 = 0x00000001,
} TEX_COORD_TYPE;

typedef enum TEX_DEPTH_COMPARE_FUNCTION {
TEX_DepthCompareFunction_Never           = 0x00000000,
TEX_DepthCompareFunction_Less            = 0x00000001,
TEX_DepthCompareFunction_Equal           = 0x00000002,
TEX_DepthCompareFunction_LessEqual       = 0x00000003,
TEX_DepthCompareFunction_Greater         = 0x00000004,
TEX_DepthCompareFunction_NotEqual        = 0x00000005,
TEX_DepthCompareFunction_GreaterEqual    = 0x00000006,
TEX_DepthCompareFunction_Always          = 0x00000007,
} TEX_DEPTH_COMPARE_FUNCTION;

typedef enum TEX_DIM {
TEX_Dim_1D                               = 0x00000000,
TEX_Dim_2D                               = 0x00000001,
TEX_Dim_3D                               = 0x00000002,
TEX_Dim_CubeMap                          = 0x00000003,
TEX_Dim_1DArray                          = 0x00000004,
TEX_Dim_2DArray                          = 0x00000005,
TEX_Dim_2D_MSAA                          = 0x00000006,
TEX_Dim_2DArray_MSAA                     = 0x00000007,
} TEX_DIM;

typedef enum TEX_FORMAT_COMP {
TEX_FormatComp_Unsigned                  = 0x00000000,
TEX_FormatComp_Signed                    = 0x00000001,
TEX_FormatComp_UnsignedBiased            = 0x00000002,
TEX_FormatComp_RESERVED_3                = 0x00000003,
} TEX_FORMAT_COMP;

typedef enum TEX_MAX_ANISO_RATIO {
TEX_MaxAnisoRatio_1to1                   = 0x00000000,
TEX_MaxAnisoRatio_2to1                   = 0x00000001,
TEX_MaxAnisoRatio_4to1                   = 0x00000002,
TEX_MaxAnisoRatio_8to1                   = 0x00000003,
TEX_MaxAnisoRatio_16to1                  = 0x00000004,
TEX_MaxAnisoRatio_RESERVED_5             = 0x00000005,
TEX_MaxAnisoRatio_RESERVED_6             = 0x00000006,
TEX_MaxAnisoRatio_RESERVED_7             = 0x00000007,
} TEX_MAX_ANISO_RATIO;

typedef enum TEX_MIP_FILTER {
TEX_MipFilter_None                       = 0x00000000,
TEX_MipFilter_Point                      = 0x00000001,
TEX_MipFilter_Linear                     = 0x00000002,
TEX_MipFilter_Point_Aniso_Adj            = 0x00000003,
} TEX_MIP_FILTER;

typedef enum TEX_REQUEST_SIZE {
TEX_RequestSize_32B                      = 0x00000000,
TEX_RequestSize_64B                      = 0x00000001,
TEX_RequestSize_128B                     = 0x00000002,
TEX_RequestSize_2X64B                    = 0x00000003,
} TEX_REQUEST_SIZE;

typedef enum TEX_SAMPLER_TYPE {
TEX_SamplerType_Invalid                  = 0x00000000,
TEX_SamplerType_Valid                    = 0x00000001,
} TEX_SAMPLER_TYPE;

typedef enum TEX_XY_FILTER {
TEX_XYFilter_Point                       = 0x00000000,
TEX_XYFilter_Linear                      = 0x00000001,
TEX_XYFilter_AnisoPoint                  = 0x00000002,
TEX_XYFilter_AnisoLinear                 = 0x00000003,
} TEX_XY_FILTER;

typedef enum TEX_Z_FILTER {
TEX_ZFilter_None                         = 0x00000000,
TEX_ZFilter_Point                        = 0x00000001,
TEX_ZFilter_Linear                       = 0x00000002,
TEX_ZFilter_RESERVED_3                   = 0x00000003,
} TEX_Z_FILTER;

typedef enum TVX_DATA_FORMAT {
TVX_FMT_INVALID                          = 0x00000000,
TVX_FMT_8                                = 0x00000001,
TVX_FMT_4_4                              = 0x00000002,
TVX_FMT_3_3_2                            = 0x00000003,
TVX_FMT_RESERVED_4                       = 0x00000004,
TVX_FMT_16                               = 0x00000005,
TVX_FMT_16_FLOAT                         = 0x00000006,
TVX_FMT_8_8                              = 0x00000007,
TVX_FMT_5_6_5                            = 0x00000008,
TVX_FMT_6_5_5                            = 0x00000009,
TVX_FMT_1_5_5_5                          = 0x0000000a,
TVX_FMT_4_4_4_4                          = 0x0000000b,
TVX_FMT_5_5_5_1                          = 0x0000000c,
TVX_FMT_32                               = 0x0000000d,
TVX_FMT_32_FLOAT                         = 0x0000000e,
TVX_FMT_16_16                            = 0x0000000f,
TVX_FMT_16_16_FLOAT                      = 0x00000010,
TVX_FMT_8_24                             = 0x00000011,
TVX_FMT_8_24_FLOAT                       = 0x00000012,
TVX_FMT_24_8                             = 0x00000013,
TVX_FMT_24_8_FLOAT                       = 0x00000014,
TVX_FMT_10_11_11                         = 0x00000015,
TVX_FMT_10_11_11_FLOAT                   = 0x00000016,
TVX_FMT_11_11_10                         = 0x00000017,
TVX_FMT_11_11_10_FLOAT                   = 0x00000018,
TVX_FMT_2_10_10_10                       = 0x00000019,
TVX_FMT_8_8_8_8                          = 0x0000001a,
TVX_FMT_10_10_10_2                       = 0x0000001b,
TVX_FMT_X24_8_32_FLOAT                   = 0x0000001c,
TVX_FMT_32_32                            = 0x0000001d,
TVX_FMT_32_32_FLOAT                      = 0x0000001e,
TVX_FMT_16_16_16_16                      = 0x0000001f,
TVX_FMT_16_16_16_16_FLOAT                = 0x00000020,
TVX_FMT_RESERVED_33                      = 0x00000021,
TVX_FMT_32_32_32_32                      = 0x00000022,
TVX_FMT_32_32_32_32_FLOAT                = 0x00000023,
TVX_FMT_RESERVED_36                      = 0x00000024,
TVX_FMT_1                                = 0x00000025,
TVX_FMT_1_REVERSED                       = 0x00000026,
TVX_FMT_GB_GR                            = 0x00000027,
TVX_FMT_BG_RG                            = 0x00000028,
TVX_FMT_32_AS_8                          = 0x00000029,
TVX_FMT_32_AS_8_8                        = 0x0000002a,
TVX_FMT_5_9_9_9_SHAREDEXP                = 0x0000002b,
TVX_FMT_8_8_8                            = 0x0000002c,
TVX_FMT_16_16_16                         = 0x0000002d,
TVX_FMT_16_16_16_FLOAT                   = 0x0000002e,
TVX_FMT_32_32_32                         = 0x0000002f,
TVX_FMT_32_32_32_FLOAT                   = 0x00000030,
TVX_FMT_BC1                              = 0x00000031,
TVX_FMT_BC2                              = 0x00000032,
TVX_FMT_BC3                              = 0x00000033,
TVX_FMT_BC4                              = 0x00000034,
TVX_FMT_BC5                              = 0x00000035,
TVX_FMT_APC0                             = 0x00000036,
TVX_FMT_APC1                             = 0x00000037,
TVX_FMT_APC2                             = 0x00000038,
TVX_FMT_APC3                             = 0x00000039,
TVX_FMT_APC4                             = 0x0000003a,
TVX_FMT_APC5                             = 0x0000003b,
TVX_FMT_APC6                             = 0x0000003c,
TVX_FMT_APC7                             = 0x0000003d,
TVX_FMT_CTX1                             = 0x0000003e,
TVX_FMT_RESERVED_63                      = 0x0000003f,
} TVX_DATA_FORMAT;

typedef enum TVX_DST_SEL {
TVX_DstSel_X                             = 0x00000000,
TVX_DstSel_Y                             = 0x00000001,
TVX_DstSel_Z                             = 0x00000002,
TVX_DstSel_W                             = 0x00000003,
TVX_DstSel_0f                            = 0x00000004,
TVX_DstSel_1f                            = 0x00000005,
TVX_DstSel_RESERVED_6                    = 0x00000006,
TVX_DstSel_Mask                          = 0x00000007,
} TVX_DST_SEL;

typedef enum TVX_ENDIAN_SWAP {
TVX_EndianSwap_None                      = 0x00000000,
TVX_EndianSwap_8in16                     = 0x00000001,
TVX_EndianSwap_8in32                     = 0x00000002,
TVX_EndianSwap_8in64                     = 0x00000003,
} TVX_ENDIAN_SWAP;

typedef enum TVX_INST {
TVX_Inst_NormalVertexFetch               = 0x00000000,
TVX_Inst_SemanticVertexFetch             = 0x00000001,
TVX_Inst_RESERVED_2                      = 0x00000002,
TVX_Inst_LD                              = 0x00000003,
TVX_Inst_GetTextureResInfo               = 0x00000004,
TVX_Inst_GetNumberOfSamples              = 0x00000005,
TVX_Inst_GetLOD                          = 0x00000006,
TVX_Inst_GetGradientsH                   = 0x00000007,
TVX_Inst_GetGradientsV                   = 0x00000008,
TVX_Inst_SetTextureOffsets               = 0x00000009,
TVX_Inst_KeepGradients                   = 0x0000000a,
TVX_Inst_SetGradientsH                   = 0x0000000b,
TVX_Inst_SetGradientsV                   = 0x0000000c,
TVX_Inst_Pass                            = 0x0000000d,
TVX_Inst_GetBufferResInfo                = 0x0000000e,
TVX_Inst_RESERVED_15                     = 0x0000000f,
TVX_Inst_Sample                          = 0x00000010,
TVX_Inst_Sample_L                        = 0x00000011,
TVX_Inst_Sample_LB                       = 0x00000012,
TVX_Inst_Sample_LZ                       = 0x00000013,
TVX_Inst_Sample_G                        = 0x00000014,
TVX_Inst_Gather4                         = 0x00000015,
TVX_Inst_Sample_G_LB                     = 0x00000016,
TVX_Inst_Gather4_O                       = 0x00000017,
TVX_Inst_Sample_C                        = 0x00000018,
TVX_Inst_Sample_C_L                      = 0x00000019,
TVX_Inst_Sample_C_LB                     = 0x0000001a,
TVX_Inst_Sample_C_LZ                     = 0x0000001b,
TVX_Inst_Sample_C_G                      = 0x0000001c,
TVX_Inst_Gather4_C                       = 0x0000001d,
TVX_Inst_Sample_C_G_LB                   = 0x0000001e,
TVX_Inst_Gather4_C_O                     = 0x0000001f,
} TVX_INST;

typedef enum TVX_NUM_FORMAT_ALL {
TVX_NumFormatAll_Norm                    = 0x00000000,
TVX_NumFormatAll_Int                     = 0x00000001,
TVX_NumFormatAll_Scaled                  = 0x00000002,
TVX_NumFormatAll_RESERVED_3              = 0x00000003,
} TVX_NUM_FORMAT_ALL;

typedef enum TVX_SRC_SEL {
TVX_SrcSel_X                             = 0x00000000,
TVX_SrcSel_Y                             = 0x00000001,
TVX_SrcSel_Z                             = 0x00000002,
TVX_SrcSel_W                             = 0x00000003,
TVX_SrcSel_0f                            = 0x00000004,
TVX_SrcSel_1f                            = 0x00000005,
} TVX_SRC_SEL;

typedef enum TVX_SRF_MODE_ALL {
TVX_SRFModeAll_ZCMO                      = 0x00000000,
TVX_SRFModeAll_NZ                        = 0x00000001,
} TVX_SRF_MODE_ALL;

typedef enum TVX_TYPE {
TVX_Type_InvalidTextureResource          = 0x00000000,
TVX_Type_InvalidVertexBuffer             = 0x00000001,
TVX_Type_ValidTextureResource            = 0x00000002,
TVX_Type_ValidVertexBuffer               = 0x00000003,
} TVX_TYPE;

typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
} TileSplit;

typedef enum TileType {
ARRAY_COLOR_TILE                         = 0x00000000,
ARRAY_DEPTH_TILE                         = 0x00000001,
} TileType;

typedef enum UTCL1FaultType {
} UTCL1FaultType;

typedef enum UTCL1RequestType {
} UTCL1RequestType;

typedef enum VGT_CACHE_INVALID_MODE {
VC_ONLY                                  = 0x00000000,
TC_ONLY                                  = 0x00000001,
VC_AND_TC                                = 0x00000002,
} VGT_CACHE_INVALID_MODE;

typedef enum VGT_DIST_MODE {
NO_DIST                                  = 0x00000000,
PATCHES                                  = 0x00000001,
DONUTS                                   = 0x00000002,
TRAPEZOIDS                               = 0x00000003,
} VGT_DIST_MODE;

typedef enum VGT_DI_INDEX_SIZE {
DI_INDEX_SIZE_16_BIT                     = 0x00000000,
DI_INDEX_SIZE_32_BIT                     = 0x00000001,
DI_INDEX_SIZE_8_BIT                      = 0x00000002,
} VGT_DI_INDEX_SIZE;

typedef enum VGT_DI_MAJOR_MODE_SELECT {
DI_MAJOR_MODE_0                          = 0x00000000,
DI_MAJOR_MODE_1                          = 0x00000001,
} VGT_DI_MAJOR_MODE_SELECT;

typedef enum VGT_DI_PRIM_TYPE {
DI_PT_NONE                               = 0x00000000,
DI_PT_POINTLIST                          = 0x00000001,
DI_PT_LINELIST                           = 0x00000002,
DI_PT_LINESTRIP                          = 0x00000003,
DI_PT_TRILIST                            = 0x00000004,
DI_PT_TRIFAN                             = 0x00000005,
DI_PT_TRISTRIP                           = 0x00000006,
DI_PT_UNUSED_1                           = 0x00000008,
DI_PT_PATCH                              = 0x00000009,
DI_PT_LINELIST_ADJ                       = 0x0000000a,
DI_PT_LINESTRIP_ADJ                      = 0x0000000b,
DI_PT_TRILIST_ADJ                        = 0x0000000c,
DI_PT_TRISTRIP_ADJ                       = 0x0000000d,
DI_PT_UNUSED_3                           = 0x0000000e,
DI_PT_UNUSED_4                           = 0x0000000f,
DI_PT_TRI_WITH_WFLAGS__GFX09             = 0x00000010,
DI_PT_RECTLIST                           = 0x00000011,
DI_PT_LINELOOP                           = 0x00000012,
DI_PT_QUADLIST                           = 0x00000013,
DI_PT_QUADSTRIP                          = 0x00000014,
DI_PT_POLYGON                            = 0x00000015,
} VGT_DI_PRIM_TYPE;

typedef enum VGT_DI_SOURCE_SELECT {
DI_SRC_SEL_DMA                           = 0x00000000,
DI_SRC_SEL_IMMEDIATE                     = 0x00000001,
DI_SRC_SEL_AUTO_INDEX                    = 0x00000002,
DI_SRC_SEL_RESERVED                      = 0x00000003,
} VGT_DI_SOURCE_SELECT;

typedef enum VGT_DMA_BUF_TYPE {
VGT_DMA_BUF_MEM                          = 0x00000000,
VGT_DMA_BUF_RING                         = 0x00000001,
VGT_DMA_BUF_SETUP                        = 0x00000002,
VGT_DMA_PTR_UPDATE                       = 0x00000003,
} VGT_DMA_BUF_TYPE;

typedef enum VGT_DMA_SWAP_MODE {
VGT_DMA_SWAP_NONE                        = 0x00000000,
VGT_DMA_SWAP_16_BIT                      = 0x00000001,
VGT_DMA_SWAP_32_BIT                      = 0x00000002,
VGT_DMA_SWAP_WORD                        = 0x00000003,
} VGT_DMA_SWAP_MODE;

typedef enum VGT_EVENT_TYPE {
Reserved_0x00                            = 0x00000000,
SAMPLE_STREAMOUTSTATS1                   = 0x00000001,
SAMPLE_STREAMOUTSTATS2                   = 0x00000002,
SAMPLE_STREAMOUTSTATS3                   = 0x00000003,
CACHE_FLUSH_TS                           = 0x00000004,
CONTEXT_DONE                             = 0x00000005,
CACHE_FLUSH                              = 0x00000006,
CS_PARTIAL_FLUSH                         = 0x00000007,
VGT_STREAMOUT_SYNC                       = 0x00000008,
VGT_STREAMOUT_RESET                      = 0x0000000a,
END_OF_PIPE_INCR_DE                      = 0x0000000b,
END_OF_PIPE_IB_END                       = 0x0000000c,
RST_PIX_CNT                              = 0x0000000d,
BREAK_BATCH                              = 0x0000000e,
VS_PARTIAL_FLUSH                         = 0x0000000f,
PS_PARTIAL_FLUSH                         = 0x00000010,
FLUSH_HS_OUTPUT                          = 0x00000011,
FLUSH_DFSM                               = 0x00000012,
RESET_TO_LOWEST_VGT                      = 0x00000013,
CACHE_FLUSH_AND_INV_TS_EVENT             = 0x00000014,
ZPASS_DONE                               = 0x00000015,
CACHE_FLUSH_AND_INV_EVENT                = 0x00000016,
PERFCOUNTER_START                        = 0x00000017,
PERFCOUNTER_STOP                         = 0x00000018,
PIPELINESTAT_START                       = 0x00000019,
PIPELINESTAT_STOP                        = 0x0000001a,
PERFCOUNTER_SAMPLE                       = 0x0000001b,
Available_0x1c__GFX09                    = 0x0000001c,
Available_0x1d__GFX09                    = 0x0000001d,
SAMPLE_PIPELINESTAT                      = 0x0000001e,
SO_VGTSTREAMOUT_FLUSH                    = 0x0000001f,
SAMPLE_STREAMOUTSTATS                    = 0x00000020,
RESET_VTX_CNT                            = 0x00000021,
BLOCK_CONTEXT_DONE                       = 0x00000022,
CS_CONTEXT_DONE                          = 0x00000023,
VGT_FLUSH                                = 0x00000024,
TGID_ROLLOVER                            = 0x00000025,
SQ_NON_EVENT                             = 0x00000026,
SC_SEND_DB_VPZ                           = 0x00000027,
BOTTOM_OF_PIPE_TS                        = 0x00000028,
FLUSH_SX_TS                              = 0x00000029,
DB_CACHE_FLUSH_AND_INV                   = 0x0000002a,
FLUSH_AND_INV_DB_DATA_TS                 = 0x0000002b,
FLUSH_AND_INV_DB_META                    = 0x0000002c,
FLUSH_AND_INV_CB_DATA_TS                 = 0x0000002d,
FLUSH_AND_INV_CB_META                    = 0x0000002e,
CS_DONE                                  = 0x0000002f,
PS_DONE                                  = 0x00000030,
FLUSH_AND_INV_CB_PIXEL_DATA              = 0x00000031,
SX_CB_RAT_ACK_REQUEST                    = 0x00000032,
THREAD_TRACE_START                       = 0x00000033,
THREAD_TRACE_STOP                        = 0x00000034,
THREAD_TRACE_MARKER                      = 0x00000035,
THREAD_TRACE_FLUSH__GFX09                = 0x00000036,
THREAD_TRACE_FINISH                      = 0x00000037,
PIXEL_PIPE_STAT_CONTROL                  = 0x00000038,
PIXEL_PIPE_STAT_DUMP                     = 0x00000039,
PIXEL_PIPE_STAT_RESET                    = 0x0000003a,
CONTEXT_SUSPEND                          = 0x0000003b,
OFFCHIP_HS_DEALLOC                       = 0x0000003c,
ENABLE_NGG_PIPELINE                      = 0x0000003d,
ENABLE_LEGACY_PIPELINE                   = 0x0000003e,
Reserved_0x3f__GFX09                     = 0x0000003f,
} VGT_EVENT_TYPE;

typedef enum VGT_GROUP_CONV_SEL {
VGT_GRP_INDEX_16                         = 0x00000000,
VGT_GRP_INDEX_32                         = 0x00000001,
VGT_GRP_UINT_16                          = 0x00000002,
VGT_GRP_UINT_32                          = 0x00000003,
VGT_GRP_SINT_16                          = 0x00000004,
VGT_GRP_SINT_32                          = 0x00000005,
VGT_GRP_FLOAT_32                         = 0x00000006,
VGT_GRP_AUTO_PRIM                        = 0x00000007,
VGT_GRP_FIX_1_23_TO_FLOAT                = 0x00000008,
} VGT_GROUP_CONV_SEL;

typedef enum VGT_GRP_PRIM_ORDER {
VGT_GRP_LIST                             = 0x00000000,
VGT_GRP_STRIP                            = 0x00000001,
VGT_GRP_FAN                              = 0x00000002,
VGT_GRP_LOOP                             = 0x00000003,
VGT_GRP_POLYGON                          = 0x00000004,
} VGT_GRP_PRIM_ORDER;

typedef enum VGT_GRP_PRIM_TYPE {
VGT_GRP_3D_POINT                         = 0x00000000,
VGT_GRP_3D_LINE                          = 0x00000001,
VGT_GRP_3D_TRI                           = 0x00000002,
VGT_GRP_3D_RECT                          = 0x00000003,
VGT_GRP_3D_QUAD                          = 0x00000004,
VGT_GRP_2D_COPY_RECT_V0                  = 0x00000005,
VGT_GRP_2D_COPY_RECT_V1                  = 0x00000006,
VGT_GRP_2D_COPY_RECT_V2                  = 0x00000007,
VGT_GRP_2D_COPY_RECT_V3                  = 0x00000008,
VGT_GRP_2D_FILL_RECT                     = 0x00000009,
VGT_GRP_2D_LINE                          = 0x0000000a,
VGT_GRP_2D_TRI                           = 0x0000000b,
VGT_GRP_PRIM_INDEX_LINE                  = 0x0000000c,
VGT_GRP_PRIM_INDEX_TRI                   = 0x0000000d,
VGT_GRP_PRIM_INDEX_QUAD                  = 0x0000000e,
VGT_GRP_3D_LINE_ADJ                      = 0x0000000f,
VGT_GRP_3D_TRI_ADJ                       = 0x00000010,
VGT_GRP_3D_PATCH                         = 0x00000011,
} VGT_GRP_PRIM_TYPE;

typedef enum VGT_GS_CUT_MODE {
GS_CUT_1024                              = 0x00000000,
GS_CUT_512                               = 0x00000001,
GS_CUT_256                               = 0x00000002,
GS_CUT_128                               = 0x00000003,
} VGT_GS_CUT_MODE;

typedef enum VGT_GS_MODE_TYPE {
GS_OFF                                   = 0x00000000,
GS_SCENARIO_A                            = 0x00000001,
GS_SCENARIO_B                            = 0x00000002,
GS_SCENARIO_G                            = 0x00000003,
GS_SCENARIO_C                            = 0x00000004,
SPRITE_EN                                = 0x00000005,
} VGT_GS_MODE_TYPE;

typedef enum VGT_GS_OUTPRIM_TYPE {
POINTLIST                                = 0x00000000,
LINESTRIP                                = 0x00000001,
TRISTRIP                                 = 0x00000002,
RECTLIST__GFX09                          = 0x00000003,
} VGT_GS_OUTPRIM_TYPE;

typedef enum VGT_INDEX_TYPE_MODE {
VGT_INDEX_16                             = 0x00000000,
VGT_INDEX_32                             = 0x00000001,
VGT_INDEX_8                              = 0x00000002,
} VGT_INDEX_TYPE_MODE;

typedef enum VGT_OUTPATH_SELECT {
VGT_OUTPATH_VTX_REUSE                    = 0x00000000,
VGT_OUTPATH_TESS_EN__GFX09               = 0x00000001,
VGT_OUTPATH_PASSTHRU__GFX09              = 0x00000002,
VGT_OUTPATH_GS_BLOCK__GFX09              = 0x00000003,
VGT_OUTPATH_HS_BLOCK__GFX09              = 0x00000004,
} VGT_OUTPATH_SELECT;

typedef enum VGT_OUT_PRIM_TYPE {
VGT_OUT_POINT                            = 0x00000000,
VGT_OUT_LINE                             = 0x00000001,
VGT_OUT_TRI                              = 0x00000002,
VGT_OUT_RECT_V0                          = 0x00000003,
VGT_OUT_RECT_V1                          = 0x00000004,
VGT_OUT_RECT_V2                          = 0x00000005,
VGT_OUT_RECT_V3                          = 0x00000006,
VGT_TE_QUAD                              = 0x00000008,
VGT_TE_PRIM_INDEX_LINE                   = 0x00000009,
VGT_TE_PRIM_INDEX_TRI                    = 0x0000000a,
VGT_TE_PRIM_INDEX_QUAD                   = 0x0000000b,
VGT_OUT_LINE_ADJ                         = 0x0000000c,
VGT_OUT_TRI_ADJ                          = 0x0000000d,
VGT_OUT_PATCH                            = 0x0000000e,
} VGT_OUT_PRIM_TYPE;

typedef enum VGT_PERFCOUNT_SELECT {
vgt_perf_VGT_SPI_ESVERT_VALID            = 0x00000001,
vgt_perf_VGT_SPI_ESVERT_EOV              = 0x00000002,
vgt_perf_VGT_SPI_ESVERT_STALLED          = 0x00000003,
vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY     = 0x00000004,
vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE     = 0x00000005,
vgt_perf_VGT_SPI_ESVERT_STATIC           = 0x00000006,
vgt_perf_VGT_SPI_GSPRIM_VALID            = 0x00000009,
vgt_perf_VGT_SPI_GSPRIM_EOV              = 0x0000000a,
vgt_perf_VGT_SPI_GSPRIM_CONT             = 0x0000000b,
vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY     = 0x0000000d,
vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE     = 0x0000000e,
vgt_perf_VGT_SPI_GSPRIM_STATIC           = 0x0000000f,
vgt_perf_VGT_SPI_VSVERT_SEND             = 0x00000014,
vgt_perf_VGT_SPI_VSVERT_EOV              = 0x00000015,
vgt_perf_VGT_SPI_VSVERT_STALLED          = 0x00000016,
vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY     = 0x00000017,
vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE     = 0x00000018,
vgt_perf_VGT_SPI_VSVERT_STATIC           = 0x00000019,
vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE      = 0x0000001c,
vgt_perf_VGT_PA_CLIPV_SEND               = 0x0000001d,
vgt_perf_VGT_PA_CLIPV_FIRSTVERT          = 0x0000001e,
vgt_perf_VGT_PA_CLIPV_STALLED            = 0x0000001f,
vgt_perf_VGT_PA_CLIPV_STARVED_BUSY       = 0x00000020,
vgt_perf_VGT_PA_CLIPV_STARVED_IDLE       = 0x00000021,
vgt_perf_VGT_PA_CLIPV_STATIC             = 0x00000022,
vgt_perf_VGT_PA_CLIPP_SEND               = 0x00000023,
vgt_perf_VGT_PA_CLIPP_EOP                = 0x00000024,
vgt_perf_VGT_PA_CLIPP_IS_EVENT           = 0x00000025,
vgt_perf_VGT_PA_CLIPP_NULL_PRIM          = 0x00000026,
vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT       = 0x00000027,
vgt_perf_VGT_PA_CLIPP_STALLED            = 0x00000028,
vgt_perf_VGT_PA_CLIPP_STARVED_BUSY       = 0x00000029,
vgt_perf_VGT_PA_CLIPP_STARVED_IDLE       = 0x0000002a,
vgt_perf_VGT_PA_CLIPP_STATIC             = 0x0000002b,
vgt_perf_VGT_PA_CLIPS_SEND               = 0x0000002c,
vgt_perf_VGT_PA_CLIPS_STALLED            = 0x0000002d,
vgt_perf_VGT_PA_CLIPS_STARVED_BUSY       = 0x0000002e,
vgt_perf_VGT_PA_CLIPS_STARVED_IDLE       = 0x0000002f,
vgt_perf_VGT_PA_CLIPS_STATIC             = 0x00000030,
vgt_perf_hs_tif_stall                    = 0x00000033,
vgt_perf_hs_input_stall                  = 0x00000034,
vgt_perf_hs_interface_stall              = 0x00000035,
vgt_perf_hs_tfm_stall                    = 0x00000036,
vgt_perf_gs_event_stall                  = 0x00000038,
vgt_perf_vgt_pa_clipp_send_not_event     = 0x00000039,
vgt_perf_vgt_pa_clipp_valid_prim         = 0x0000003a,
vgt_perf_vgt_busy                        = 0x00000040,
vgt_perf_vgt_gs_busy                     = 0x00000041,
vgt_perf_gsprim_stalled                  = 0x00000042,
vgt_perf_esvert_stalled_gs_tbl           = 0x00000043,
vgt_perf_esvert_stalled_gs_event         = 0x00000044,
vgt_perf_gsprim_stalled_gs_tbl           = 0x00000047,
vgt_perf_gsprim_stalled_gs_event         = 0x00000048,
vgt_perf_gsprim_stalled_esvert           = 0x00000049,
vgt_perf_counters_avail_stalled          = 0x0000004c,
vgt_perf_gs_rb_space_avail_stalled       = 0x0000004d,
vgt_perf_gs_issue_rtr_stalled            = 0x0000004e,
vgt_perf_strmout_stalled                 = 0x00000050,
vgt_perf_cm_stalled_by_gog               = 0x00000052,
vgt_perf_cm_reading_stalled              = 0x00000053,
vgt_perf_cm_stalled_by_gsfetch_done      = 0x00000054,
vgt_perf_gog_vs_tbl_stalled              = 0x00000055,
vgt_perf_gog_out_indx_stalled            = 0x00000056,
vgt_perf_gog_out_prim_stalled            = 0x00000057,
vgt_perf_waveid_stalled                  = 0x00000058,
vgt_perf_gog_busy                        = 0x00000059,
vgt_perf_sclk_reg_vld_event              = 0x0000005b,
vgt_perf_vs_conflicting_indices          = 0x0000005c,
vgt_perf_sclk_core_vld_event             = 0x0000005d,
vgt_perf_sclk_gs_vld_event               = 0x0000005f,
vgt_perf_ds_prims                        = 0x00000072,
vgt_perf_hs_thread_groups                = 0x00000075,
vgt_perf_vs_thread_groups                = 0x00000077,
vgt_perf_gs_done_latency                 = 0x0000007b,
vgt_perf_vgt_hs_busy                     = 0x0000007c,
vgt_perf_vgt_te11_busy                   = 0x0000007d,
vgt_perf_hs_flush                        = 0x0000007f,
vgt_perf_vgt_pa_clipp_eopg               = 0x00000081,
vgt_perf_gs_done                         = 0x00000085,
vgt_perf_gs_done_received                = 0x00000087,
vgt_perf_gs_ring_high_water_mark         = 0x00000089,
vgt_perf_vs_table_high_water_mark        = 0x0000008a,
vgt_perf_hs_tgs_active_high_water_mark   = 0x0000008b,
vgt_perf_pa_clipp_dealloc                = 0x0000008c,
vgt_perf_cut_mem_flush_stalled           = 0x0000008d,
vgt_perf_vsvert_work_received            = 0x0000008e,
vgt_perf_vgt_pa_clipp_starved_after_work = 0x0000008f,
vgt_perf_te11_con_starved_after_work     = 0x00000090,
vgt_perf_sclk_te11_vld                   = 0x00000093,
} VGT_PERFCOUNT_SELECT;

typedef enum VGT_RDREQ_POLICY {
VGT_POLICY_LRU                           = 0x00000000,
VGT_POLICY_STREAM                        = 0x00000001,
} VGT_RDREQ_POLICY;

typedef enum VGT_STAGES_ES_EN {
ES_STAGE_OFF                             = 0x00000000,
ES_STAGE_DS                              = 0x00000001,
ES_STAGE_REAL                            = 0x00000002,
RESERVED_ES                              = 0x00000003,
} VGT_STAGES_ES_EN;

typedef enum VGT_STAGES_GS_EN {
GS_STAGE_OFF                             = 0x00000000,
GS_STAGE_ON                              = 0x00000001,
} VGT_STAGES_GS_EN;

typedef enum VGT_STAGES_HS_EN {
HS_STAGE_OFF                             = 0x00000000,
HS_STAGE_ON                              = 0x00000001,
} VGT_STAGES_HS_EN;

typedef enum VGT_STAGES_LS_EN {
LS_STAGE_OFF                             = 0x00000000,
LS_STAGE_ON                              = 0x00000001,
CS_STAGE_ON                              = 0x00000002,
RESERVED_LS                              = 0x00000003,
} VGT_STAGES_LS_EN;

typedef enum VGT_STAGES_VS_EN {
VS_STAGE_REAL                            = 0x00000000,
VS_STAGE_DS                              = 0x00000001,
VS_STAGE_COPY_SHADER                     = 0x00000002,
RESERVED_VS                              = 0x00000003,
} VGT_STAGES_VS_EN;

typedef enum VGT_TESS_PARTITION {
PART_INTEGER                             = 0x00000000,
PART_POW2                                = 0x00000001,
PART_FRAC_ODD                            = 0x00000002,
PART_FRAC_EVEN                           = 0x00000003,
} VGT_TESS_PARTITION;

typedef enum VGT_TESS_TOPOLOGY {
OUTPUT_POINT                             = 0x00000000,
OUTPUT_LINE                              = 0x00000001,
OUTPUT_TRIANGLE_CW                       = 0x00000002,
OUTPUT_TRIANGLE_CCW                      = 0x00000003,
} VGT_TESS_TOPOLOGY;

typedef enum VGT_TESS_TYPE {
TESS_ISOLINE                             = 0x00000000,
TESS_TRIANGLE                            = 0x00000001,
TESS_QUAD                                = 0x00000002,
} VGT_TESS_TYPE;

typedef enum VTX_CLAMP {
VTX_Clamp_ClampToZero                    = 0x00000000,
VTX_Clamp_ClampToNAN                     = 0x00000001,
} VTX_CLAMP;

typedef enum VTX_FETCH_TYPE {
VTX_FetchType_VertexData                 = 0x00000000,
VTX_FetchType_InstanceData               = 0x00000001,
VTX_FetchType_NoIndexOffset              = 0x00000002,
VTX_FetchType_RESERVED_3                 = 0x00000003,
} VTX_FETCH_TYPE;

typedef enum VTX_FORMAT_COMP_ALL {
VTX_FormatCompAll_Unsigned               = 0x00000000,
VTX_FormatCompAll_Signed                 = 0x00000001,
} VTX_FORMAT_COMP_ALL;

typedef enum VTX_MEM_REQUEST_SIZE {
VTX_MemRequestSize_32B                   = 0x00000000,
VTX_MemRequestSize_64B                   = 0x00000001,
} VTX_MEM_REQUEST_SIZE;

typedef enum WD_IA_DRAW_REG_XFER {
} WD_IA_DRAW_REG_XFER;

typedef enum WD_IA_DRAW_SOURCE {
WD_IA_DRAW_SOURCE_DMA                    = 0x00000000,
WD_IA_DRAW_SOURCE_IMMD                   = 0x00000001,
WD_IA_DRAW_SOURCE_AUTO                   = 0x00000002,
WD_IA_DRAW_SOURCE_OPAQ                   = 0x00000003,
} WD_IA_DRAW_SOURCE;

typedef enum WD_IA_DRAW_TYPE {
WD_IA_DRAW_TYPE_DI_MM0                   = 0x00000000,
WD_IA_DRAW_TYPE_EVENT_INIT               = 0x00000002,
WD_IA_DRAW_TYPE_EVENT_ADDR               = 0x00000003,
WD_IA_DRAW_TYPE_MIN_INDX                 = 0x00000004,
WD_IA_DRAW_TYPE_MAX_INDX                 = 0x00000005,
WD_IA_DRAW_TYPE_INDX_OFF                 = 0x00000006,
WD_IA_DRAW_TYPE_IMM_DATA                 = 0x00000007,
} WD_IA_DRAW_TYPE;

typedef enum WD_PERFCOUNT_SELECT {
wd_perf_wd_busy                          = 0x00000005,
wd_perf_wd_sclk_reg_vld_event            = 0x00000006,
wd_perf_wd_sclk_input_vld_event          = 0x00000007,
wd_perf_wd_sclk_core_vld_event           = 0x00000008,
wd_perf_inside_tf_bin_0                  = 0x0000000a,
wd_perf_inside_tf_bin_1                  = 0x0000000b,
wd_perf_inside_tf_bin_2                  = 0x0000000c,
wd_perf_inside_tf_bin_3                  = 0x0000000d,
wd_perf_inside_tf_bin_4                  = 0x0000000e,
wd_perf_inside_tf_bin_5                  = 0x0000000f,
wd_perf_inside_tf_bin_6                  = 0x00000010,
wd_perf_inside_tf_bin_7                  = 0x00000011,
wd_perf_inside_tf_bin_8                  = 0x00000012,
wd_perf_tfreq_lat_bin_0                  = 0x00000013,
wd_perf_tfreq_lat_bin_1                  = 0x00000014,
wd_perf_tfreq_lat_bin_2                  = 0x00000015,
wd_perf_tfreq_lat_bin_3                  = 0x00000016,
wd_perf_tfreq_lat_bin_4                  = 0x00000017,
wd_perf_tfreq_lat_bin_5                  = 0x00000018,
wd_perf_tfreq_lat_bin_6                  = 0x00000019,
wd_perf_tfreq_lat_bin_7                  = 0x0000001a,
wd_starved_on_hs_done                    = 0x0000001b,
wd_perf_se0_hs_done_latency              = 0x0000001c,
wd_perf_se1_hs_done_latency              = 0x0000001d,
wd_perf_se2_hs_done_latency              = 0x0000001e,
wd_perf_se3_hs_done_latency              = 0x0000001f,
wd_perf_hs_done_se0                      = 0x00000020,
wd_perf_hs_done_se1                      = 0x00000021,
wd_perf_hs_done_se2                      = 0x00000022,
wd_perf_hs_done_se3                      = 0x00000023,
wd_perf_null_patches                     = 0x00000024,
wd_perf_utcl1_stall_utcl2_event          = 0x00000039,
} WD_PERFCOUNT_SELECT;

typedef enum ZFormat {
Z_INVALID                                = 0x00000000,
Z_16                                     = 0x00000001,
Z_24                                     = 0x00000002,
Z_32_FLOAT                               = 0x00000003,
} ZFormat;

typedef enum ZLimitSumm {
FORCE_SUMM_OFF                           = 0x00000000,
FORCE_SUMM_MINZ                          = 0x00000001,
FORCE_SUMM_MAXZ                          = 0x00000002,
FORCE_SUMM_BOTH                          = 0x00000003,
} ZLimitSumm;

typedef enum ZModeForce {
NO_FORCE                                 = 0x00000000,
FORCE_EARLY_Z                            = 0x00000001,
FORCE_LATE_Z                             = 0x00000002,
FORCE_RE_Z                               = 0x00000003,
} ZModeForce;

typedef enum ZOrder {
LATE_Z                                   = 0x00000000,
EARLY_Z_THEN_LATE_Z                      = 0x00000001,
RE_Z                                     = 0x00000002,
EARLY_Z_THEN_RE_Z                        = 0x00000003,
} ZOrder;

typedef enum ZSamplePosition {
Z_SAMPLE_CENTER                          = 0x00000000,
Z_SAMPLE_CENTROID                        = 0x00000001,
} ZSamplePosition;

typedef enum ZpassControl {
ZPASS_DISABLE                            = 0x00000000,
ZPASS_SAMPLES                            = 0x00000001,
ZPASS_PIXELS                             = 0x00000002,
} ZpassControl;

//Merged Enumerations
typedef enum ACV_WAVE_CMD_ACTION {
ACV_WAVE_CMD_ACTION_LAUNCH               = 0x00000000,
ACV_WAVE_CMD_ACTION_HALT                 = 0x00000001,
ACV_WAVE_CMD_ACTION_KILL                 = 0x00000002,
ACV_WAVE_CMD_ACTION_DEBUG                = 0x00000003,
ACV_WAVE_CMD_ACTION_RESUME               = 0x00000004,
ACV_WAVE_CMD_ACTION_STEP                 = 0x00000005,
ACV_WAVE_CMD_ACTION_TRAP                 = 0x00000006,
} ACV_WAVE_CMD_ACTION;

typedef enum BUF_FMT {
BUF_FMT_INVALID                          = 0x00000000,
BUF_FMT_8_UNORM                          = 0x00000001,
BUF_FMT_8_SNORM                          = 0x00000002,
BUF_FMT_8_USCALED                        = 0x00000003,
BUF_FMT_8_SSCALED                        = 0x00000004,
BUF_FMT_8_UINT                           = 0x00000005,
BUF_FMT_8_SINT                           = 0x00000006,
BUF_FMT_16_UNORM                         = 0x00000007,
BUF_FMT_16_SNORM                         = 0x00000008,
BUF_FMT_16_USCALED                       = 0x00000009,
BUF_FMT_16_SSCALED                       = 0x0000000a,
BUF_FMT_16_UINT                          = 0x0000000b,
BUF_FMT_16_SINT                          = 0x0000000c,
BUF_FMT_16_FLOAT                         = 0x0000000d,
BUF_FMT_8_8_UNORM                        = 0x0000000e,
BUF_FMT_8_8_SNORM                        = 0x0000000f,
BUF_FMT_8_8_USCALED                      = 0x00000010,
BUF_FMT_8_8_SSCALED                      = 0x00000011,
BUF_FMT_8_8_UINT                         = 0x00000012,
BUF_FMT_8_8_SINT                         = 0x00000013,
BUF_FMT_32_UINT                          = 0x00000014,
BUF_FMT_32_SINT                          = 0x00000015,
BUF_FMT_32_FLOAT                         = 0x00000016,
BUF_FMT_16_16_UNORM                      = 0x00000017,
BUF_FMT_16_16_SNORM                      = 0x00000018,
BUF_FMT_16_16_USCALED                    = 0x00000019,
BUF_FMT_16_16_SSCALED                    = 0x0000001a,
BUF_FMT_16_16_UINT                       = 0x0000001b,
BUF_FMT_16_16_SINT                       = 0x0000001c,
BUF_FMT_16_16_FLOAT                      = 0x0000001d,
BUF_FMT_10_11_11_UNORM                   = 0x0000001e,
BUF_FMT_10_11_11_SNORM                   = 0x0000001f,
BUF_FMT_10_11_11_USCALED                 = 0x00000020,
BUF_FMT_10_11_11_SSCALED                 = 0x00000021,
BUF_FMT_10_11_11_UINT                    = 0x00000022,
BUF_FMT_10_11_11_SINT                    = 0x00000023,
BUF_FMT_10_11_11_FLOAT                   = 0x00000024,
BUF_FMT_11_11_10_UNORM                   = 0x00000025,
BUF_FMT_11_11_10_SNORM                   = 0x00000026,
BUF_FMT_11_11_10_USCALED                 = 0x00000027,
BUF_FMT_11_11_10_SSCALED                 = 0x00000028,
BUF_FMT_11_11_10_UINT                    = 0x00000029,
BUF_FMT_11_11_10_SINT                    = 0x0000002a,
BUF_FMT_11_11_10_FLOAT                   = 0x0000002b,
BUF_FMT_10_10_10_2_UNORM                 = 0x0000002c,
BUF_FMT_10_10_10_2_SNORM                 = 0x0000002d,
BUF_FMT_10_10_10_2_USCALED               = 0x0000002e,
BUF_FMT_10_10_10_2_SSCALED               = 0x0000002f,
BUF_FMT_10_10_10_2_UINT                  = 0x00000030,
BUF_FMT_10_10_10_2_SINT                  = 0x00000031,
BUF_FMT_2_10_10_10_UNORM                 = 0x00000032,
BUF_FMT_2_10_10_10_SNORM                 = 0x00000033,
BUF_FMT_2_10_10_10_USCALED               = 0x00000034,
BUF_FMT_2_10_10_10_SSCALED               = 0x00000035,
BUF_FMT_2_10_10_10_UINT                  = 0x00000036,
BUF_FMT_2_10_10_10_SINT                  = 0x00000037,
BUF_FMT_8_8_8_8_UNORM                    = 0x00000038,
BUF_FMT_8_8_8_8_SNORM                    = 0x00000039,
BUF_FMT_8_8_8_8_USCALED                  = 0x0000003a,
BUF_FMT_8_8_8_8_SSCALED                  = 0x0000003b,
BUF_FMT_8_8_8_8_UINT                     = 0x0000003c,
BUF_FMT_8_8_8_8_SINT                     = 0x0000003d,
BUF_FMT_32_32_UINT                       = 0x0000003e,
BUF_FMT_32_32_SINT                       = 0x0000003f,
BUF_FMT_32_32_FLOAT                      = 0x00000040,
BUF_FMT_16_16_16_16_UNORM                = 0x00000041,
BUF_FMT_16_16_16_16_SNORM                = 0x00000042,
BUF_FMT_16_16_16_16_USCALED              = 0x00000043,
BUF_FMT_16_16_16_16_SSCALED              = 0x00000044,
BUF_FMT_16_16_16_16_UINT                 = 0x00000045,
BUF_FMT_16_16_16_16_SINT                 = 0x00000046,
BUF_FMT_16_16_16_16_FLOAT                = 0x00000047,
BUF_FMT_32_32_32_UINT                    = 0x00000048,
BUF_FMT_32_32_32_SINT                    = 0x00000049,
BUF_FMT_32_32_32_FLOAT                   = 0x0000004a,
BUF_FMT_32_32_32_32_UINT                 = 0x0000004b,
BUF_FMT_32_32_32_32_SINT                 = 0x0000004c,
BUF_FMT_32_32_32_32_FLOAT                = 0x0000004d,
BUF_FMT_RESERVED_78                      = 0x0000004e,
BUF_FMT_RESERVED_79                      = 0x0000004f,
BUF_FMT_RESERVED_80                      = 0x00000050,
BUF_FMT_RESERVED_81                      = 0x00000051,
BUF_FMT_RESERVED_82                      = 0x00000052,
BUF_FMT_RESERVED_83                      = 0x00000053,
BUF_FMT_RESERVED_84                      = 0x00000054,
BUF_FMT_RESERVED_85                      = 0x00000055,
BUF_FMT_RESERVED_86                      = 0x00000056,
BUF_FMT_RESERVED_87                      = 0x00000057,
BUF_FMT_RESERVED_88                      = 0x00000058,
BUF_FMT_RESERVED_89                      = 0x00000059,
BUF_FMT_RESERVED_90                      = 0x0000005a,
BUF_FMT_RESERVED_91                      = 0x0000005b,
BUF_FMT_RESERVED_92                      = 0x0000005c,
BUF_FMT_RESERVED_93                      = 0x0000005d,
BUF_FMT_RESERVED_94                      = 0x0000005e,
BUF_FMT_RESERVED_95                      = 0x0000005f,
BUF_FMT_RESERVED_96                      = 0x00000060,
BUF_FMT_RESERVED_97                      = 0x00000061,
BUF_FMT_RESERVED_98                      = 0x00000062,
BUF_FMT_RESERVED_99                      = 0x00000063,
BUF_FMT_RESERVED_100                     = 0x00000064,
BUF_FMT_RESERVED_101                     = 0x00000065,
BUF_FMT_RESERVED_102                     = 0x00000066,
BUF_FMT_RESERVED_103                     = 0x00000067,
BUF_FMT_RESERVED_104                     = 0x00000068,
BUF_FMT_RESERVED_105                     = 0x00000069,
BUF_FMT_RESERVED_106                     = 0x0000006a,
BUF_FMT_RESERVED_107                     = 0x0000006b,
BUF_FMT_RESERVED_108                     = 0x0000006c,
BUF_FMT_RESERVED_109                     = 0x0000006d,
BUF_FMT_RESERVED_110                     = 0x0000006e,
BUF_FMT_RESERVED_111                     = 0x0000006f,
BUF_FMT_RESERVED_112                     = 0x00000070,
BUF_FMT_RESERVED_113                     = 0x00000071,
BUF_FMT_RESERVED_114                     = 0x00000072,
BUF_FMT_RESERVED_115                     = 0x00000073,
BUF_FMT_RESERVED_116                     = 0x00000074,
BUF_FMT_RESERVED_117                     = 0x00000075,
BUF_FMT_RESERVED_118                     = 0x00000076,
BUF_FMT_RESERVED_119                     = 0x00000077,
BUF_FMT_RESERVED_120                     = 0x00000078,
BUF_FMT_RESERVED_121                     = 0x00000079,
BUF_FMT_RESERVED_122                     = 0x0000007a,
BUF_FMT_RESERVED_123                     = 0x0000007b,
BUF_FMT_RESERVED_124                     = 0x0000007c,
BUF_FMT_RESERVED_125                     = 0x0000007d,
BUF_FMT_RESERVED_126                     = 0x0000007e,
BUF_FMT_RESERVED_127                     = 0x0000007f,
} BUF_FMT;

typedef enum BinMapMode {
BIN_MAP_MODE_NONE                        = 0x00000000,
BIN_MAP_MODE_RTA_INDEX                   = 0x00000001,
BIN_MAP_MODE_POPS                        = 0x00000002,
} BinMapMode;

typedef enum CHA_PERF_SEL {
CHA_PERF_SEL_BUSY                        = 0x00000000,
CHA_PERF_SEL_STALL_CHC0                  = 0x00000001,
CHA_PERF_SEL_STALL_CHC1                  = 0x00000002,
CHA_PERF_SEL_STALL_CHC2                  = 0x00000003,
CHA_PERF_SEL_STALL_CHC3                  = 0x00000004,
CHA_PERF_SEL_STALL_CHC4                  = 0x00000005,
CHA_PERF_SEL_STALL_CHC5                  = 0x00000006,
CHA_PERF_SEL_REQUEST_CHC0                = 0x00000007,
CHA_PERF_SEL_REQUEST_CHC1                = 0x00000008,
CHA_PERF_SEL_REQUEST_CHC2                = 0x00000009,
CHA_PERF_SEL_REQUEST_CHC3                = 0x0000000a,
CHA_PERF_SEL_REQUEST_CHC4                = 0x0000000b,
CHA_PERF_SEL_MEM_32B_WDS_CHC0            = 0x0000000c,
CHA_PERF_SEL_MEM_32B_WDS_CHC1            = 0x0000000d,
CHA_PERF_SEL_MEM_32B_WDS_CHC2            = 0x0000000e,
CHA_PERF_SEL_MEM_32B_WDS_CHC3            = 0x0000000f,
CHA_PERF_SEL_MEM_32B_WDS_CHC4            = 0x00000010,
CHA_PERF_SEL_IO_32B_WDS_CHC0             = 0x00000011,
CHA_PERF_SEL_IO_32B_WDS_CHC1             = 0x00000012,
CHA_PERF_SEL_IO_32B_WDS_CHC2             = 0x00000013,
CHA_PERF_SEL_IO_32B_WDS_CHC3             = 0x00000014,
CHA_PERF_SEL_IO_32B_WDS_CHC4             = 0x00000015,
CHA_PERF_SEL_MEM_BURST_COUNT_CHC0        = 0x00000016,
CHA_PERF_SEL_MEM_BURST_COUNT_CHC1        = 0x00000017,
CHA_PERF_SEL_MEM_BURST_COUNT_CHC2        = 0x00000018,
CHA_PERF_SEL_MEM_BURST_COUNT_CHC3        = 0x00000019,
CHA_PERF_SEL_MEM_BURST_COUNT_CHC4        = 0x0000001a,
CHA_PERF_SEL_IO_BURST_COUNT_CHC0         = 0x0000001b,
CHA_PERF_SEL_IO_BURST_COUNT_CHC1         = 0x0000001c,
CHA_PERF_SEL_IO_BURST_COUNT_CHC2         = 0x0000001d,
CHA_PERF_SEL_IO_BURST_COUNT_CHC3         = 0x0000001e,
CHA_PERF_SEL_IO_BURST_COUNT_CHC4         = 0x0000001f,
CHA_PERF_SEL_ARB_REQUESTS                = 0x00000020,
CHA_PERF_SEL_REQ_ARB_LEVEL_CHC0          = 0x00000021,
CHA_PERF_SEL_REQ_ARB_LEVEL_CHC1          = 0x00000022,
CHA_PERF_SEL_REQ_ARB_LEVEL_CHC2          = 0x00000023,
CHA_PERF_SEL_REQ_ARB_LEVEL_CHC3          = 0x00000024,
CHA_PERF_SEL_REQ_ARB_LEVEL_CHC4          = 0x00000025,
CHA_PERF_SEL_REQ_INFLIGHT_LEVEL          = 0x00000026,
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0     = 0x00000027,
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1     = 0x00000028,
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2     = 0x00000029,
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3     = 0x0000002a,
CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4     = 0x0000002b,
CHA_PERF_SEL_CYCLE                       = 0x0000002c,
} CHA_PERF_SEL;

typedef enum CHCG_PERF_SEL {
CHCG_PERF_SEL_CYCLE                      = 0x00000000,
CHCG_PERF_SEL_BUSY                       = 0x00000001,
CHCG_PERF_SEL_ARB_RET_LEVEL              = 0x00000002,
CHCG_PERF_SEL_GL2_REQ_READ_LATENCY       = 0x00000003,
CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY      = 0x00000004,
CHCG_PERF_SEL_REQ                        = 0x00000005,
CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET        = 0x00000006,
CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET     = 0x00000007,
CHCG_PERF_SEL_REQ_NOP_ACK                = 0x00000008,
CHCG_PERF_SEL_REQ_NOP_RTN0               = 0x00000009,
CHCG_PERF_SEL_REQ_READ                   = 0x0000000a,
CHCG_PERF_SEL_REQ_READ_128B              = 0x0000000b,
CHCG_PERF_SEL_REQ_READ_32B               = 0x0000000c,
CHCG_PERF_SEL_REQ_READ_64B               = 0x0000000d,
CHCG_PERF_SEL_REQ_WRITE                  = 0x0000000e,
CHCG_PERF_SEL_REQ_WRITE_32B              = 0x0000000f,
CHCG_PERF_SEL_REQ_WRITE_64B              = 0x00000010,
CHCG_PERF_SEL_STALL_GUS_GL1              = 0x00000011,
CHCG_PERF_SEL_STALL_BUFFER_FULL          = 0x00000012,
CHCG_PERF_SEL_REQ_CLIENT0                = 0x00000013,
CHCG_PERF_SEL_REQ_CLIENT1                = 0x00000014,
CHCG_PERF_SEL_REQ_CLIENT2                = 0x00000015,
CHCG_PERF_SEL_REQ_CLIENT3                = 0x00000016,
CHCG_PERF_SEL_REQ_CLIENT4                = 0x00000017,
CHCG_PERF_SEL_REQ_CLIENT5                = 0x00000018,
CHCG_PERF_SEL_REQ_CLIENT6                = 0x00000019,
CHCG_PERF_SEL_REQ_CLIENT7                = 0x0000001a,
CHCG_PERF_SEL_REQ_CLIENT8                = 0x0000001b,
CHCG_PERF_SEL_REQ_CLIENT9                = 0x0000001c,
CHCG_PERF_SEL_REQ_CLIENT10               = 0x0000001d,
CHCG_PERF_SEL_REQ_CLIENT11               = 0x0000001e,
CHCG_PERF_SEL_REQ_CLIENT12               = 0x0000001f,
CHCG_PERF_SEL_REQ_CLIENT13               = 0x00000020,
CHCG_PERF_SEL_REQ_CLIENT14               = 0x00000021,
} CHCG_PERF_SEL;

typedef enum CHC_PERF_SEL {
CHC_PERF_SEL_CYCLE                       = 0x00000000,
CHC_PERF_SEL_BUSY                        = 0x00000001,
CHC_PERF_SEL_ARB_RET_LEVEL               = 0x00000002,
CHC_PERF_SEL_GL2_REQ_READ_LATENCY        = 0x00000003,
CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY       = 0x00000004,
CHC_PERF_SEL_REQ                         = 0x00000005,
CHC_PERF_SEL_REQ_ATOMIC_WITH_RET         = 0x00000006,
CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET      = 0x00000007,
CHC_PERF_SEL_REQ_NOP_ACK                 = 0x00000008,
CHC_PERF_SEL_REQ_NOP_RTN0                = 0x00000009,
CHC_PERF_SEL_REQ_READ                    = 0x0000000a,
CHC_PERF_SEL_REQ_READ_128B               = 0x0000000b,
CHC_PERF_SEL_REQ_READ_32B                = 0x0000000c,
CHC_PERF_SEL_REQ_READ_64B                = 0x0000000d,
CHC_PERF_SEL_REQ_WRITE                   = 0x0000000e,
CHC_PERF_SEL_REQ_WRITE_32B               = 0x0000000f,
CHC_PERF_SEL_REQ_WRITE_64B               = 0x00000010,
CHC_PERF_SEL_STALL_GL2_GL1               = 0x00000011,
CHC_PERF_SEL_STALL_BUFFER_FULL           = 0x00000012,
CHC_PERF_SEL_REQ_CLIENT0                 = 0x00000013,
CHC_PERF_SEL_REQ_CLIENT1                 = 0x00000014,
CHC_PERF_SEL_REQ_CLIENT2                 = 0x00000015,
CHC_PERF_SEL_REQ_CLIENT3                 = 0x00000016,
CHC_PERF_SEL_REQ_CLIENT4                 = 0x00000017,
CHC_PERF_SEL_REQ_CLIENT5                 = 0x00000018,
CHC_PERF_SEL_REQ_CLIENT6                 = 0x00000019,
CHC_PERF_SEL_REQ_CLIENT7                 = 0x0000001a,
CHC_PERF_SEL_REQ_CLIENT8                 = 0x0000001b,
CHC_PERF_SEL_REQ_CLIENT9                 = 0x0000001c,
CHC_PERF_SEL_REQ_CLIENT10                = 0x0000001d,
CHC_PERF_SEL_REQ_CLIENT11                = 0x0000001e,
CHC_PERF_SEL_REQ_CLIENT12                = 0x0000001f,
CHC_PERF_SEL_REQ_CLIENT13                = 0x00000020,
CHC_PERF_SEL_REQ_CLIENT14                = 0x00000021,
} CHC_PERF_SEL;

typedef enum CPC_LATENCY_STATS_SEL {
CPC_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
CPC_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
CPC_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
CPC_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
CPC_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
CPC_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
CPC_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000006,
CPC_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000007,
CPC_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000008,
} CPC_LATENCY_STATS_SEL;

typedef enum CPF_LATENCY_STATS_SEL {
CPF_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
CPF_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
CPF_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
CPF_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
CPF_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
CPF_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
CPF_LATENCY_STATS_SEL_READ_MAX           = 0x00000006,
CPF_LATENCY_STATS_SEL_READ_MIN           = 0x00000007,
CPF_LATENCY_STATS_SEL_READ_LAST          = 0x00000008,
CPF_LATENCY_STATS_SEL_INVAL_MAX          = 0x00000009,
CPF_LATENCY_STATS_SEL_INVAL_MIN          = 0x0000000a,
CPF_LATENCY_STATS_SEL_INVAL_LAST         = 0x0000000b,
} CPF_LATENCY_STATS_SEL;

typedef enum CPF_PERFCOUNTWINDOW_SEL {
CPF_PERFWINDOW_SEL_CSF                   = 0x00000000,
CPF_PERFWINDOW_SEL_HQD1                  = 0x00000001,
CPF_PERFWINDOW_SEL_HQD2                  = 0x00000002,
CPF_PERFWINDOW_SEL_RDMA                  = 0x00000003,
CPF_PERFWINDOW_SEL_RWPP                  = 0x00000004,
} CPF_PERFCOUNTWINDOW_SEL;

typedef enum CPG_LATENCY_STATS_SEL {
CPG_LATENCY_STATS_SEL_XACK_MAX           = 0x00000000,
CPG_LATENCY_STATS_SEL_XACK_MIN           = 0x00000001,
CPG_LATENCY_STATS_SEL_XACK_LAST          = 0x00000002,
CPG_LATENCY_STATS_SEL_XNACK_MAX          = 0x00000003,
CPG_LATENCY_STATS_SEL_XNACK_MIN          = 0x00000004,
CPG_LATENCY_STATS_SEL_XNACK_LAST         = 0x00000005,
CPG_LATENCY_STATS_SEL_WRITE_MAX          = 0x00000006,
CPG_LATENCY_STATS_SEL_WRITE_MIN          = 0x00000007,
CPG_LATENCY_STATS_SEL_WRITE_LAST         = 0x00000008,
CPG_LATENCY_STATS_SEL_READ_MAX           = 0x00000009,
CPG_LATENCY_STATS_SEL_READ_MIN           = 0x0000000a,
CPG_LATENCY_STATS_SEL_READ_LAST          = 0x0000000b,
CPG_LATENCY_STATS_SEL_ATOMIC_MAX         = 0x0000000c,
CPG_LATENCY_STATS_SEL_ATOMIC_MIN         = 0x0000000d,
CPG_LATENCY_STATS_SEL_ATOMIC_LAST        = 0x0000000e,
CPG_LATENCY_STATS_SEL_INVAL_MAX          = 0x0000000f,
CPG_LATENCY_STATS_SEL_INVAL_MIN          = 0x00000010,
CPG_LATENCY_STATS_SEL_INVAL_LAST         = 0x00000011,
} CPG_LATENCY_STATS_SEL;

typedef enum CPG_PERFCOUNTWINDOW_SEL {
CPG_PERFWINDOW_SEL_PFP                   = 0x00000000,
CPG_PERFWINDOW_SEL_ME                    = 0x00000001,
CPG_PERFWINDOW_SEL_CE                    = 0x00000002,
CPG_PERFWINDOW_SEL_MES                   = 0x00000003,
CPG_PERFWINDOW_SEL_MEC1                  = 0x00000004,
CPG_PERFWINDOW_SEL_MEC2                  = 0x00000005,
CPG_PERFWINDOW_SEL_DFY                   = 0x00000006,
CPG_PERFWINDOW_SEL_DMA                   = 0x00000007,
CPG_PERFWINDOW_SEL_SHADOW                = 0x00000008,
CPG_PERFWINDOW_SEL_RB                    = 0x00000009,
CPG_PERFWINDOW_SEL_CEDMA                 = 0x0000000a,
CPG_PERFWINDOW_SEL_PRT_HDR_RPTR          = 0x0000000b,
CPG_PERFWINDOW_SEL_PRT_SMP_RPTR          = 0x0000000c,
CPG_PERFWINDOW_SEL_PQ1                   = 0x0000000d,
CPG_PERFWINDOW_SEL_PQ2                   = 0x0000000e,
CPG_PERFWINDOW_SEL_PQ3                   = 0x0000000f,
CPG_PERFWINDOW_SEL_MEMWR                 = 0x00000010,
CPG_PERFWINDOW_SEL_MEMRD                 = 0x00000011,
CPG_PERFWINDOW_SEL_VGT0                  = 0x00000012,
CPG_PERFWINDOW_SEL_VGT1                  = 0x00000013,
CPG_PERFWINDOW_SEL_APPEND                = 0x00000014,
CPG_PERFWINDOW_SEL_QURD                  = 0x00000015,
CPG_PERFWINDOW_SEL_DDID                  = 0x00000016,
CPG_PERFWINDOW_SEL_SR                    = 0x00000017,
CPG_PERFWINDOW_SEL_QU_EOP                = 0x00000018,
CPG_PERFWINDOW_SEL_QU_STRM               = 0x00000019,
CPG_PERFWINDOW_SEL_QU_PIPE               = 0x0000001a,
CPG_PERFWINDOW_SEL_RESERVED1             = 0x0000001b,
CPG_PERFWINDOW_SEL_CPC_IC                = 0x0000001c,
CPG_PERFWINDOW_SEL_RESERVED2             = 0x0000001d,
CPG_PERFWINDOW_SEL_CPG_IC                = 0x0000001e,
} CPG_PERFCOUNTWINDOW_SEL;

typedef enum CP_DDID_CNTL_MODE {
STALL                                    = 0x00000000,
OVERRUN                                  = 0x00000001,
} CP_DDID_CNTL_MODE;

typedef enum CP_DDID_CNTL_SIZE {
SIZE_8K                                  = 0x00000000,
SIZE_16K                                 = 0x00000001,
} CP_DDID_CNTL_SIZE;

typedef enum CP_DDID_CNTL_VMID_SEL {
DDID_VMID_PIPE                           = 0x00000000,
DDID_VMID_CNTL                           = 0x00000001,
} CP_DDID_CNTL_VMID_SEL;

typedef enum CSCNTL_TYPE {
CSCNTL_TYPE_TG                           = 0x00000000,
CSCNTL_TYPE_STATE                        = 0x00000001,
CSCNTL_TYPE_EVENT                        = 0x00000002,
CSCNTL_TYPE_PRIVATE                      = 0x00000003,
} CSCNTL_TYPE;

typedef enum DSM_DATA_SEL {
DSM_DATA_SEL_DISABLE                     = 0x00000000,
DSM_DATA_SEL_0                           = 0x00000001,
DSM_DATA_SEL_1                           = 0x00000002,
DSM_DATA_SEL_BOTH                        = 0x00000003,
} DSM_DATA_SEL;

typedef enum FullTileWaveBreak {
FULL_TILE_WAVE_BREAK_NBC_ONLY            = 0x00000000,
FULL_TILE_WAVE_BREAK_BOTH                = 0x00000001,
FULL_TILE_WAVE_BREAK_NONE                = 0x00000002,
FULL_TILE_WAVE_BREAK_BC_ONLY             = 0x00000003,
} FullTileWaveBreak;

typedef enum GCRPerfSel {
GCR_PERF_SEL_NONE                        = 0x00000000,
GCR_PERF_SEL_SDMA0_ALL_REQ               = 0x00000001,
GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ         = 0x00000002,
GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ   = 0x00000003,
GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ     = 0x00000004,
GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ   = 0x00000005,
GCR_PERF_SEL_SDMA0_GL2_ALL_REQ           = 0x00000006,
GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ         = 0x00000007,
GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ   = 0x00000008,
GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ     = 0x00000009,
GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ   = 0x0000000a,
GCR_PERF_SEL_SDMA0_GL1_ALL_REQ           = 0x0000000b,
GCR_PERF_SEL_SDMA0_METADATA_REQ          = 0x0000000c,
GCR_PERF_SEL_SDMA0_SQC_DATA_REQ          = 0x0000000d,
GCR_PERF_SEL_SDMA0_SQC_INST_REQ          = 0x0000000e,
GCR_PERF_SEL_SDMA0_TCP_REQ               = 0x0000000f,
GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010,
GCR_PERF_SEL_SDMA1_ALL_REQ               = 0x00000011,
GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ         = 0x00000012,
GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ   = 0x00000013,
GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ     = 0x00000014,
GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ   = 0x00000015,
GCR_PERF_SEL_SDMA1_GL2_ALL_REQ           = 0x00000016,
GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ         = 0x00000017,
GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ   = 0x00000018,
GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ     = 0x00000019,
GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ   = 0x0000001a,
GCR_PERF_SEL_SDMA1_GL1_ALL_REQ           = 0x0000001b,
GCR_PERF_SEL_SDMA1_METADATA_REQ          = 0x0000001c,
GCR_PERF_SEL_SDMA1_SQC_DATA_REQ          = 0x0000001d,
GCR_PERF_SEL_SDMA1_SQC_INST_REQ          = 0x0000001e,
GCR_PERF_SEL_SDMA1_TCP_REQ               = 0x0000001f,
GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020,
GCR_PERF_SEL_CPG_ALL_REQ                 = 0x00000021,
GCR_PERF_SEL_CPG_GL2_RANGE_REQ           = 0x00000022,
GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ     = 0x00000023,
GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ       = 0x00000024,
GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ     = 0x00000025,
GCR_PERF_SEL_CPG_GL2_ALL_REQ             = 0x00000026,
GCR_PERF_SEL_CPG_GL1_RANGE_REQ           = 0x00000027,
GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ     = 0x00000028,
GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ       = 0x00000029,
GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ     = 0x0000002a,
GCR_PERF_SEL_CPG_GL1_ALL_REQ             = 0x0000002b,
GCR_PERF_SEL_CPG_METADATA_REQ            = 0x0000002c,
GCR_PERF_SEL_CPG_SQC_DATA_REQ            = 0x0000002d,
GCR_PERF_SEL_CPG_SQC_INST_REQ            = 0x0000002e,
GCR_PERF_SEL_CPG_TCP_REQ                 = 0x0000002f,
GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ   = 0x00000030,
GCR_PERF_SEL_CPC_ALL_REQ                 = 0x00000031,
GCR_PERF_SEL_CPC_GL2_RANGE_REQ           = 0x00000032,
GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ     = 0x00000033,
GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ       = 0x00000034,
GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ     = 0x00000035,
GCR_PERF_SEL_CPC_GL2_ALL_REQ             = 0x00000036,
GCR_PERF_SEL_CPC_GL1_RANGE_REQ           = 0x00000037,
GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ     = 0x00000038,
GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ       = 0x00000039,
GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ     = 0x0000003a,
GCR_PERF_SEL_CPC_GL1_ALL_REQ             = 0x0000003b,
GCR_PERF_SEL_CPC_METADATA_REQ            = 0x0000003c,
GCR_PERF_SEL_CPC_SQC_DATA_REQ            = 0x0000003d,
GCR_PERF_SEL_CPC_SQC_INST_REQ            = 0x0000003e,
GCR_PERF_SEL_CPC_TCP_REQ                 = 0x0000003f,
GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ   = 0x00000040,
GCR_PERF_SEL_CPF_ALL_REQ                 = 0x00000041,
GCR_PERF_SEL_CPF_GL2_RANGE_REQ           = 0x00000042,
GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ     = 0x00000043,
GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ       = 0x00000044,
GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ     = 0x00000045,
GCR_PERF_SEL_CPF_GL2_ALL_REQ             = 0x00000046,
GCR_PERF_SEL_CPF_GL1_RANGE_REQ           = 0x00000047,
GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ     = 0x00000048,
GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ       = 0x00000049,
GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ     = 0x0000004a,
GCR_PERF_SEL_CPF_GL1_ALL_REQ             = 0x0000004b,
GCR_PERF_SEL_CPF_METADATA_REQ            = 0x0000004c,
GCR_PERF_SEL_CPF_SQC_DATA_REQ            = 0x0000004d,
GCR_PERF_SEL_CPF_SQC_INST_REQ            = 0x0000004e,
GCR_PERF_SEL_CPF_TCP_REQ                 = 0x0000004f,
GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ   = 0x00000050,
GCR_PERF_SEL_VIRT_REQ                    = 0x00000051,
GCR_PERF_SEL_PHY_REQ                     = 0x00000052,
GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ     = 0x00000053,
GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ     = 0x00000054,
GCR_PERF_SEL_ALL_REQ                     = 0x00000055,
GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056,
GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057,
GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058,
GCR_PERF_SEL_UTCL2_REQ                   = 0x00000059,
GCR_PERF_SEL_UTCL2_RET                   = 0x0000005a,
GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT   = 0x0000005b,
GCR_PERF_SEL_UTCL2_INFLIGHT_REQ          = 0x0000005c,
GCR_PERF_SEL_UTCL2_FILTERED_RET          = 0x0000005d,
} GCRPerfSel;

typedef enum GE_PERFCOUNT_SELECT {
ge_assembler_busy                        = 0x00000000,
ge_assembler_stalled                     = 0x00000001,
ge_cm_reading_stalled                    = 0x00000002,
ge_cm_stalled_by_gog                     = 0x00000003,
ge_cm_stalled_by_gsfetch_done            = 0x00000004,
ge_dma_busy                              = 0x00000005,
ge_dma_lat_bin_0                         = 0x00000006,
ge_dma_lat_bin_1                         = 0x00000007,
ge_dma_lat_bin_2                         = 0x00000008,
ge_dma_lat_bin_3                         = 0x00000009,
ge_dma_lat_bin_4                         = 0x0000000a,
ge_dma_lat_bin_5                         = 0x0000000b,
ge_dma_lat_bin_6                         = 0x0000000c,
ge_dma_lat_bin_7                         = 0x0000000d,
ge_dma_return_cl0                        = 0x0000000e,
ge_dma_return_cl1                        = 0x0000000f,
ge_dma_utcl1_consecutive_retry_event     = 0x00000010,
ge_dma_utcl1_request_event               = 0x00000011,
ge_dma_utcl1_retry_event                 = 0x00000012,
ge_dma_utcl1_stall_event                 = 0x00000013,
ge_dma_utcl1_stall_utcl2_event           = 0x00000014,
ge_dma_utcl1_translation_hit_event       = 0x00000015,
ge_dma_utcl1_translation_miss_event      = 0x00000016,
ge_ds_cache_hits                         = 0x00000017,
ge_ds_prims                              = 0x00000018,
ge_es_done                               = 0x00000019,
ge_es_done_latency                       = 0x0000001a,
ge_es_flush                              = 0x0000001b,
ge_es_ring_high_water_mark               = 0x0000001c,
ge_es_thread_groups                      = 0x0000001d,
ge_esthread_stalled_es_rb_full           = 0x0000001e,
ge_esthread_stalled_spi_bp               = 0x0000001f,
ge_esvert_stalled_gs_event               = 0x00000020,
ge_esvert_stalled_gs_tbl                 = 0x00000021,
ge_esvert_stalled_gsprim                 = 0x00000022,
ge_assembler_dma_starved                 = 0x00000023,
ge_gog_busy                              = 0x00000024,
ge_gog_out_indx_stalled                  = 0x00000025,
ge_gog_out_prim_stalled                  = 0x00000026,
ge_gog_vs_tbl_stalled                    = 0x00000027,
ge_gs_cache_hits                         = 0x00000028,
ge_gs_counters_avail_stalled             = 0x00000029,
ge_gs_done                               = 0x0000002a,
ge_gs_done_latency                       = 0x0000002b,
ge_gs_issue_rtr_stalled                  = 0x0000002c,
ge_gs_rb_space_avail_stalled             = 0x0000002d,
ge_gs_ring_high_water_mark               = 0x0000002e,
ge_gsprim_stalled_es_tbl                 = 0x0000002f,
ge_gsprim_stalled_esvert                 = 0x00000030,
ge_gsprim_stalled_gs_event               = 0x00000031,
ge_gsprim_stalled_gs_tbl                 = 0x00000032,
ge_gsthread_stalled                      = 0x00000033,
ge_hs_done                               = 0x00000034,
ge_hs_done_latency                       = 0x00000035,
ge_hs_done_se0                           = 0x00000036,
ge_hs_done_se1                           = 0x00000037,
ge_hs_done_se2_reserved                  = 0x00000038,
ge_hs_done_se3_reserved                  = 0x00000039,
ge_hs_tfm_stall                          = 0x0000003a,
ge_hs_tgs_active_high_water_mark         = 0x0000003b,
ge_hs_thread_groups                      = 0x0000003c,
ge_inside_tf_bin_0                       = 0x0000003d,
ge_inside_tf_bin_1                       = 0x0000003e,
ge_inside_tf_bin_2                       = 0x0000003f,
ge_inside_tf_bin_3                       = 0x00000040,
ge_inside_tf_bin_4                       = 0x00000041,
ge_inside_tf_bin_5                       = 0x00000042,
ge_inside_tf_bin_6                       = 0x00000043,
ge_inside_tf_bin_7                       = 0x00000044,
ge_inside_tf_bin_8                       = 0x00000045,
ge_ls_done                               = 0x00000046,
ge_ls_done_latency                       = 0x00000047,
ge_null_patch                            = 0x00000048,
ge_se0pa0_clipp_eop                      = 0x00000049,
ge_se0pa0_clipp_eopg                     = 0x0000004a,
ge_se0pa0_clipp_is_event                 = 0x0000004b,
ge_se0pa0_clipp_new_vtx_vect             = 0x0000004c,
ge_se0pa0_clipp_null_prim                = 0x0000004d,
ge_se0pa0_clipp_send                     = 0x0000004e,
ge_se0pa0_clipp_send_not_event           = 0x0000004f,
ge_se0pa0_clipp_stalled                  = 0x00000050,
ge_se0pa0_clipp_starved_busy             = 0x00000051,
ge_se0pa0_clipp_starved_after_work       = 0x00000052,
ge_se0pa0_clipp_valid_prim               = 0x00000053,
ge_se0pa0_clips_send                     = 0x00000054,
ge_se0pa0_clips_stalled                  = 0x00000055,
ge_se0pa0_clipv_send                     = 0x00000056,
ge_se0pa0_clipv_stalled                  = 0x00000057,
ge_se0pa1_clipp_eop                      = 0x00000058,
ge_se0pa1_clipp_eopg                     = 0x00000059,
ge_se0pa1_clipp_is_event                 = 0x0000005a,
ge_se0pa1_clipp_new_vtx_vect             = 0x0000005b,
ge_se0pa1_clipp_null_prim                = 0x0000005c,
ge_se0pa1_clipp_send                     = 0x0000005d,
ge_se0pa1_clipp_send_not_event           = 0x0000005e,
ge_se0pa1_clipp_stalled                  = 0x0000005f,
ge_se0pa1_clipp_starved_busy             = 0x00000060,
ge_se0pa1_clipp_starved_after_work       = 0x00000061,
ge_se0pa1_clipp_valid_prim               = 0x00000062,
ge_se0pa1_clips_send                     = 0x00000063,
ge_se0pa1_clips_stalled                  = 0x00000064,
ge_se0pa1_clipv_send                     = 0x00000065,
ge_se0pa1_clipv_stalled                  = 0x00000066,
ge_se1pa0_clipp_eop                      = 0x00000067,
ge_se1pa0_clipp_eopg                     = 0x00000068,
ge_se1pa0_clipp_is_event                 = 0x00000069,
ge_se1pa0_clipp_new_vtx_vect             = 0x0000006a,
ge_se1pa0_clipp_null_prim                = 0x0000006b,
ge_se1pa0_clipp_send                     = 0x0000006c,
ge_se1pa0_clipp_send_not_event           = 0x0000006d,
ge_se1pa0_clipp_stalled                  = 0x0000006e,
ge_se1pa0_clipp_starved_busy             = 0x0000006f,
ge_se1pa0_clipp_starved_after_work       = 0x00000070,
ge_se1pa0_clipp_valid_prim               = 0x00000071,
ge_se1pa0_clips_send                     = 0x00000072,
ge_se1pa0_clips_stalled                  = 0x00000073,
ge_se1pa0_clipv_send                     = 0x00000074,
ge_se1pa0_clipv_stalled                  = 0x00000075,
ge_se1pa1_clipp_eop                      = 0x00000076,
ge_se1pa1_clipp_eopg                     = 0x00000077,
ge_se1pa1_clipp_is_event                 = 0x00000078,
ge_se1pa1_clipp_new_vtx_vect             = 0x00000079,
ge_se1pa1_clipp_null_prim                = 0x0000007a,
ge_se1pa1_clipp_send                     = 0x0000007b,
ge_se1pa1_clipp_send_not_event           = 0x0000007c,
ge_se1pa1_clipp_stalled                  = 0x0000007d,
ge_se1pa1_clipp_starved_busy             = 0x0000007e,
ge_se1pa1_clipp_starved_after_work       = 0x0000007f,
ge_se1pa1_clipp_valid_prim               = 0x00000080,
ge_se1pa1_clips_send                     = 0x00000081,
ge_se1pa1_clips_stalled                  = 0x00000082,
ge_se1pa1_clipv_send                     = 0x00000083,
ge_se1pa1_clipv_stalled                  = 0x00000084,
ge_se2pa0_clipp_eop                      = 0x00000085,
ge_se2pa0_clipp_eopg                     = 0x00000086,
ge_se2pa0_clipp_is_event                 = 0x00000087,
ge_se2pa0_clipp_new_vtx_vect             = 0x00000088,
ge_se2pa0_clipp_null_prim                = 0x00000089,
ge_se2pa0_clipp_send                     = 0x0000008a,
ge_se2pa0_clipp_send_not_event           = 0x0000008b,
ge_se2pa0_clipp_stalled                  = 0x0000008c,
ge_se2pa0_clipp_starved_busy             = 0x0000008d,
ge_se2pa0_clipp_starved_after_work       = 0x0000008e,
ge_se2pa0_clipp_valid_prim               = 0x0000008f,
ge_se2pa0_clips_send                     = 0x00000090,
ge_se2pa0_clips_stalled                  = 0x00000091,
ge_se2pa0_clipv_send                     = 0x00000092,
ge_se2pa0_clipv_stalled                  = 0x00000093,
ge_se2pa1_clipp_eop                      = 0x00000094,
ge_se2pa1_clipp_eopg                     = 0x00000095,
ge_se2pa1_clipp_is_event                 = 0x00000096,
ge_se2pa1_clipp_new_vtx_vect             = 0x00000097,
ge_se2pa1_clipp_null_prim                = 0x00000098,
ge_se2pa1_clipp_send                     = 0x00000099,
ge_se2pa1_clipp_send_not_event           = 0x0000009a,
ge_se2pa1_clipp_stalled                  = 0x0000009b,
ge_se2pa1_clipp_starved_busy             = 0x0000009c,
ge_se2pa1_clipp_starved_after_work       = 0x0000009d,
ge_se2pa1_clipp_valid_prim               = 0x0000009e,
ge_se2pa1_clips_send                     = 0x0000009f,
ge_se2pa1_clips_stalled                  = 0x000000a0,
ge_se2pa1_clipv_send                     = 0x000000a1,
ge_se2pa1_clipv_stalled                  = 0x000000a2,
ge_se3pa0_clipp_eop                      = 0x000000a3,
ge_se3pa0_clipp_eopg                     = 0x000000a4,
ge_se3pa0_clipp_is_event                 = 0x000000a5,
ge_se3pa0_clipp_new_vtx_vect             = 0x000000a6,
ge_se3pa0_clipp_null_prim                = 0x000000a7,
ge_se3pa0_clipp_send                     = 0x000000a8,
ge_se3pa0_clipp_send_not_event           = 0x000000a9,
ge_se3pa0_clipp_stalled                  = 0x000000aa,
ge_se3pa0_clipp_starved_busy             = 0x000000ab,
ge_se3pa0_clipp_starved_after_work       = 0x000000ac,
ge_se3pa0_clipp_valid_prim               = 0x000000ad,
ge_se3pa0_clips_send                     = 0x000000ae,
ge_se3pa0_clips_stalled                  = 0x000000af,
ge_se3pa0_clipv_send                     = 0x000000b0,
ge_se3pa0_clipv_stalled                  = 0x000000b1,
ge_se3pa1_clipp_eop                      = 0x000000b2,
ge_se3pa1_clipp_eopg                     = 0x000000b3,
ge_se3pa1_clipp_is_event                 = 0x000000b4,
ge_se3pa1_clipp_new_vtx_vect             = 0x000000b5,
ge_se3pa1_clipp_null_prim                = 0x000000b6,
ge_se3pa1_clipp_send                     = 0x000000b7,
ge_se3pa1_clipp_send_not_event           = 0x000000b8,
ge_se3pa1_clipp_stalled                  = 0x000000b9,
ge_se3pa1_clipp_starved_busy             = 0x000000ba,
ge_se3pa1_clipp_starved_after_work       = 0x000000bb,
ge_se3pa1_clipp_valid_prim               = 0x000000bc,
ge_se3pa1_clips_send                     = 0x000000bd,
ge_se3pa1_clips_stalled                  = 0x000000be,
ge_se3pa1_clipv_send                     = 0x000000bf,
ge_se3pa1_clipv_stalled                  = 0x000000c0,
ge_rbiu_di_fifo_stalled                  = 0x000000c1,
ge_rbiu_di_fifo_starved                  = 0x000000c2,
ge_rbiu_dr_fifo_stalled                  = 0x000000c3,
ge_rbiu_dr_fifo_starved                  = 0x000000c4,
ge_reused_es_indices                     = 0x000000c5,
ge_reused_vs_indices                     = 0x000000c6,
ge_sclk_core_vld                         = 0x000000c7,
ge_sclk_gs_vld                           = 0x000000c8,
ge_sclk_input_vld                        = 0x000000c9,
ge_sclk_leg_gs_arb_vld                   = 0x000000ca,
ge_sclk_ngg_vld                          = 0x000000cb,
ge_sclk_reg_vld                          = 0x000000cc,
ge_sclk_te11_vld                         = 0x000000cd,
ge_sclk_vr_vld                           = 0x000000ce,
ge_sclk_wd_te11_vld                      = 0x000000cf,
ge_spi_esvert_eov                        = 0x000000d0,
ge_spi_esvert_stalled                    = 0x000000d1,
ge_spi_esvert_starved_busy               = 0x000000d2,
ge_spi_esvert_valid                      = 0x000000d3,
ge_spi_eswave_is_event                   = 0x000000d4,
ge_spi_eswave_send                       = 0x000000d5,
ge_se0spi_gsprim_cont                    = 0x000000d6,
ge_se1spi_gsprim_cont                    = 0x000000d7,
ge_se2spi_gsprim_cont                    = 0x000000d8,
ge_se3spi_gsprim_cont                    = 0x000000d9,
ge_spi_gsprim_eov                        = 0x000000da,
ge_spi_gsprim_stalled                    = 0x000000db,
ge_spi_gsprim_starved_busy               = 0x000000dc,
ge_spi_gsprim_valid                      = 0x000000dd,
ge_spi_gssubgrp_is_event                 = 0x000000de,
ge_spi_gssubgrp_send                     = 0x000000df,
ge_spi_hsvert_eov                        = 0x000000e0,
ge_spi_hsvert_stalled                    = 0x000000e1,
ge_spi_hsvert_starved_busy               = 0x000000e2,
ge_spi_hsvert_valid                      = 0x000000e3,
ge_spi_hswave_is_event                   = 0x000000e4,
ge_spi_hswave_send                       = 0x000000e5,
ge_spi_lsvert_eov                        = 0x000000e6,
ge_spi_lsvert_stalled                    = 0x000000e7,
ge_spi_lsvert_starved_busy               = 0x000000e8,
ge_spi_lsvert_valid                      = 0x000000e9,
ge_spi_lswave_is_event                   = 0x000000ea,
ge_spi_lswave_send                       = 0x000000eb,
ge_spi_vsvert_eov                        = 0x000000ec,
ge_spi_vsvert_send                       = 0x000000ed,
ge_spi_vsvert_stalled                    = 0x000000ee,
ge_spi_vsvert_starved_busy               = 0x000000ef,
ge_spi_vswave_is_event                   = 0x000000f0,
ge_spi_vswave_send                       = 0x000000f1,
ge_starved_on_hs_done                    = 0x000000f2,
ge_stat_busy                             = 0x000000f3,
ge_stat_combined_busy                    = 0x000000f4,
ge_stat_no_dma_busy                      = 0x000000f5,
ge_strmout_stalled                       = 0x000000f6,
ge_te11_busy                             = 0x000000f7,
ge_te11_starved                          = 0x000000f8,
ge_tfreq_lat_bin_0                       = 0x000000f9,
ge_tfreq_lat_bin_1                       = 0x000000fa,
ge_tfreq_lat_bin_2                       = 0x000000fb,
ge_tfreq_lat_bin_3                       = 0x000000fc,
ge_tfreq_lat_bin_4                       = 0x000000fd,
ge_tfreq_lat_bin_5                       = 0x000000fe,
ge_tfreq_lat_bin_6                       = 0x000000ff,
ge_tfreq_lat_bin_7                       = 0x00000100,
ge_tfreq_utcl1_consecutive_retry_event   = 0x00000101,
ge_tfreq_utcl1_request_event             = 0x00000102,
ge_tfreq_utcl1_retry_event               = 0x00000103,
ge_tfreq_utcl1_stall_event               = 0x00000104,
ge_tfreq_utcl1_stall_utcl2_event         = 0x00000105,
ge_tfreq_utcl1_translation_hit_event     = 0x00000106,
ge_tfreq_utcl1_translation_miss_event    = 0x00000107,
ge_ls_thread_group                       = 0x00000108,
ge_rcm_indicies_hit                      = 0x00000109,
ge_vs_cache_hits                         = 0x0000010a,
ge_vs_done                               = 0x0000010b,
ge_vs_pc_stall                           = 0x0000010c,
ge_vs_table_high_water_mark              = 0x0000010d,
ge_vs_thread_groups                      = 0x0000010e,
ge_vsvert_api_send                       = 0x0000010f,
ge_vsvert_ds_send                        = 0x00000110,
ge_wait_for_es_done_stalled              = 0x00000111,
ge_waveid_stalled                        = 0x00000112,
ge_spi_vsvert_valid                      = 0x00000113,
pc_feorder_fifo_full                     = 0x00000114,
pc_ge_manager_busy                       = 0x00000115,
pc_req_stall_se0                         = 0x00000116,
pc_req_stall_se1                         = 0x00000117,
pc_req_stall_se2                         = 0x00000118,
pc_req_stall_se3                         = 0x00000119,
ge_pipe0_to_pipe1                        = 0x0000011a,
ge_pipe1_to_pipe0                        = 0x0000011b,
ge_dma_return_size_cl0                   = 0x0000011c,
ge_dma_return_size_cl1                   = 0x0000011d,
ge_spi_gssubgrp_event_window_active      = 0x0000011e,
ge_bypass_fifo_full                      = 0x0000011f,
ge_hs_input_stall0                       = 0x00000120,
ge_hs_input_stall1                       = 0x00000121,
ge_pc_space_zero                         = 0x00000122,
} GE_PERFCOUNT_SELECT;

typedef enum GL0V_CACHE_POLICIES {
GL0V_CACHE_POLICY_MISS_LRU               = 0x00000000,
GL0V_CACHE_POLICY_MISS_EVICT             = 0x00000001,
GL0V_CACHE_POLICY_HIT_LRU                = 0x00000002,
GL0V_CACHE_POLICY_HIT_EVICT              = 0x00000003,
} GL0V_CACHE_POLICIES;

typedef enum GL1A_PERF_SEL {
GL1A_PERF_SEL_BUSY                       = 0x00000000,
GL1A_PERF_SEL_STALL_GL1C0                = 0x00000001,
GL1A_PERF_SEL_STALL_GL1C1                = 0x00000002,
GL1A_PERF_SEL_STALL_GL1C2                = 0x00000003,
GL1A_PERF_SEL_STALL_GL1C3                = 0x00000004,
GL1A_PERF_SEL_STALL_GL1C4                = 0x00000005,
GL1A_PERF_SEL_REQUEST_GL1C0              = 0x00000006,
GL1A_PERF_SEL_REQUEST_GL1C1              = 0x00000007,
GL1A_PERF_SEL_REQUEST_GL1C2              = 0x00000008,
GL1A_PERF_SEL_REQUEST_GL1C3              = 0x00000009,
GL1A_PERF_SEL_REQUEST_GL1C4              = 0x0000000a,
GL1A_PERF_SEL_MEM_32B_WDS_GL1C0          = 0x0000000b,
GL1A_PERF_SEL_MEM_32B_WDS_GL1C1          = 0x0000000c,
GL1A_PERF_SEL_MEM_32B_WDS_GL1C2          = 0x0000000d,
GL1A_PERF_SEL_MEM_32B_WDS_GL1C3          = 0x0000000e,
GL1A_PERF_SEL_MEM_32B_WDS_GL1C4          = 0x0000000f,
GL1A_PERF_SEL_IO_32B_WDS_GL1C0           = 0x00000010,
GL1A_PERF_SEL_IO_32B_WDS_GL1C1           = 0x00000011,
GL1A_PERF_SEL_IO_32B_WDS_GL1C2           = 0x00000012,
GL1A_PERF_SEL_IO_32B_WDS_GL1C3           = 0x00000013,
GL1A_PERF_SEL_IO_32B_WDS_GL1C4           = 0x00000014,
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0      = 0x00000015,
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1      = 0x00000016,
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2      = 0x00000017,
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3      = 0x00000018,
GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4      = 0x00000019,
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0       = 0x0000001a,
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1       = 0x0000001b,
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2       = 0x0000001c,
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3       = 0x0000001d,
GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4       = 0x0000001e,
GL1A_PERF_SEL_ARB_REQUESTS               = 0x0000001f,
GL1A_PERF_SEL_REQ_ARB_LEVEL_GL1C0        = 0x00000020,
GL1A_PERF_SEL_REQ_ARB_LEVEL_GL1C1        = 0x00000021,
GL1A_PERF_SEL_REQ_ARB_LEVEL_GL1C2        = 0x00000022,
GL1A_PERF_SEL_REQ_ARB_LEVEL_GL1C3        = 0x00000023,
GL1A_PERF_SEL_REQ_ARB_LEVEL_GL1C4        = 0x00000024,
GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL         = 0x00000025,
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0   = 0x00000026,
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1   = 0x00000027,
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2   = 0x00000028,
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3   = 0x00000029,
GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4   = 0x0000002a,
GL1A_PERF_SEL_CYCLE                      = 0x0000002b,
} GL1A_PERF_SEL;

typedef enum GL1CG_PERF_SEL {
GL1CG_PERF_SEL_CYCLE                     = 0x00000000,
GL1CG_PERF_SEL_BUSY                      = 0x00000001,
GL1CG_PERF_SEL_ARB_RET_LEVEL             = 0x00000002,
GL1CG_PERF_SEL_GL2_REQ_READ_LATENCY      = 0x00000003,
GL1CG_PERF_SEL_GL2_REQ_WRITE_LATENCY     = 0x00000004,
GL1CG_PERF_SEL_REQ                       = 0x00000005,
GL1CG_PERF_SEL_REQ_ATOMIC_WITH_RET       = 0x00000006,
GL1CG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET    = 0x00000007,
GL1CG_PERF_SEL_REQ_NOP_ACK               = 0x00000008,
GL1CG_PERF_SEL_REQ_NOP_RTN0              = 0x00000009,
GL1CG_PERF_SEL_REQ_READ                  = 0x0000000a,
GL1CG_PERF_SEL_REQ_READ_128B             = 0x0000000b,
GL1CG_PERF_SEL_REQ_READ_32B              = 0x0000000c,
GL1CG_PERF_SEL_REQ_READ_64B              = 0x0000000d,
GL1CG_PERF_SEL_REQ_WRITE                 = 0x0000000e,
GL1CG_PERF_SEL_REQ_WRITE_32B             = 0x0000000f,
GL1CG_PERF_SEL_REQ_WRITE_64B             = 0x00000010,
GL1CG_PERF_SEL_STALL_GUS_GL1             = 0x00000011,
GL1CG_PERF_SEL_STALL_BUFFER_FULL         = 0x00000012,
GL1CG_PERF_SEL_REQ_CLIENT0               = 0x00000013,
GL1CG_PERF_SEL_REQ_CLIENT1               = 0x00000014,
GL1CG_PERF_SEL_REQ_CLIENT2               = 0x00000015,
GL1CG_PERF_SEL_REQ_CLIENT3               = 0x00000016,
GL1CG_PERF_SEL_REQ_CLIENT4               = 0x00000017,
GL1CG_PERF_SEL_REQ_CLIENT5               = 0x00000018,
GL1CG_PERF_SEL_REQ_CLIENT6               = 0x00000019,
GL1CG_PERF_SEL_REQ_CLIENT7               = 0x0000001a,
GL1CG_PERF_SEL_REQ_CLIENT8               = 0x0000001b,
GL1CG_PERF_SEL_REQ_CLIENT9               = 0x0000001c,
GL1CG_PERF_SEL_REQ_CLIENT10              = 0x0000001d,
GL1CG_PERF_SEL_REQ_CLIENT11              = 0x0000001e,
GL1CG_PERF_SEL_REQ_CLIENT12              = 0x0000001f,
GL1CG_PERF_SEL_REQ_CLIENT13              = 0x00000020,
GL1CG_PERF_SEL_REQ_CLIENT14              = 0x00000021,
GL1CG_PERF_SEL_REQ_CLIENT15              = 0x00000022,
GL1CG_PERF_SEL_REQ_CLIENT16              = 0x00000023,
GL1CG_PERF_SEL_REQ_CLIENT17              = 0x00000024,
GL1CG_PERF_SEL_REQ_CLIENT18              = 0x00000025,
} GL1CG_PERF_SEL;

typedef enum GL1C_PERF_SEL {
GL1C_PERF_SEL_CYCLE                      = 0x00000000,
GL1C_PERF_SEL_BUSY                       = 0x00000001,
GL1C_PERF_SEL_ARB_RET_LEVEL              = 0x00000002,
GL1C_PERF_SEL_GL2_REQ_READ               = 0x00000003,
GL1C_PERF_SEL_GL2_REQ_READ_128B          = 0x00000004,
GL1C_PERF_SEL_GL2_REQ_READ_32B           = 0x00000005,
GL1C_PERF_SEL_GL2_REQ_READ_64B           = 0x00000006,
GL1C_PERF_SEL_GL2_REQ_READ_LATENCY       = 0x00000007,
GL1C_PERF_SEL_GL2_REQ_WRITE              = 0x00000008,
GL1C_PERF_SEL_GL2_REQ_WRITE_32B          = 0x00000009,
GL1C_PERF_SEL_GL2_REQ_WRITE_64B          = 0x0000000a,
GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY      = 0x0000000b,
GL1C_PERF_SEL_GL2_REQ_PREFETCH           = 0x0000000c,
GL1C_PERF_SEL_REQ                        = 0x0000000d,
GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET        = 0x0000000e,
GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET     = 0x0000000f,
GL1C_PERF_SEL_REQ_SHADER_INV             = 0x00000010,
GL1C_PERF_SEL_REQ_MISS                   = 0x00000011,
GL1C_PERF_SEL_REQ_NOP_ACK                = 0x00000012,
GL1C_PERF_SEL_REQ_NOP_RTN0               = 0x00000013,
GL1C_PERF_SEL_REQ_READ                   = 0x00000014,
GL1C_PERF_SEL_REQ_READ_128B              = 0x00000015,
GL1C_PERF_SEL_REQ_READ_32B               = 0x00000016,
GL1C_PERF_SEL_REQ_READ_64B               = 0x00000017,
GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT  = 0x00000018,
GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU    = 0x00000019,
GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 0x0000001a,
GL1C_PERF_SEL_REQ_WRITE                  = 0x0000001b,
GL1C_PERF_SEL_REQ_WRITE_32B              = 0x0000001c,
GL1C_PERF_SEL_REQ_WRITE_64B              = 0x0000001d,
GL1C_PERF_SEL_STALL_GL2_GL1              = 0x0000001e,
GL1C_PERF_SEL_STALL_LFIFO_FULL           = 0x0000001f,
GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 0x00000020,
GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE  = 0x00000021,
GL1C_PERF_SEL_STALL_GCR_INV              = 0x00000022,
GL1C_PERF_SEL_REQ_CLIENT0                = 0x00000023,
GL1C_PERF_SEL_REQ_CLIENT1                = 0x00000024,
GL1C_PERF_SEL_REQ_CLIENT2                = 0x00000025,
GL1C_PERF_SEL_REQ_CLIENT3                = 0x00000026,
GL1C_PERF_SEL_REQ_CLIENT4                = 0x00000027,
GL1C_PERF_SEL_REQ_CLIENT5                = 0x00000028,
GL1C_PERF_SEL_REQ_CLIENT6                = 0x00000029,
GL1C_PERF_SEL_REQ_CLIENT7                = 0x0000002a,
GL1C_PERF_SEL_REQ_CLIENT8                = 0x0000002b,
GL1C_PERF_SEL_REQ_CLIENT9                = 0x0000002c,
GL1C_PERF_SEL_REQ_CLIENT10               = 0x0000002d,
GL1C_PERF_SEL_REQ_CLIENT11               = 0x0000002e,
GL1C_PERF_SEL_REQ_CLIENT12               = 0x0000002f,
GL1C_PERF_SEL_REQ_CLIENT13               = 0x00000030,
GL1C_PERF_SEL_REQ_CLIENT14               = 0x00000031,
GL1C_PERF_SEL_REQ_CLIENT15               = 0x00000032,
GL1C_PERF_SEL_REQ_CLIENT16               = 0x00000033,
GL1C_PERF_SEL_REQ_CLIENT17               = 0x00000034,
GL1C_PERF_SEL_REQ_CLIENT18               = 0x00000035,
} GL1C_PERF_SEL;

typedef enum GL1_CACHE_POLICIES {
GL1_CACHE_POLICY_MISS_LRU                = 0x00000000,
GL1_CACHE_POLICY_MISS_EVICT              = 0x00000001,
GL1_CACHE_POLICY_HIT_LRU                 = 0x00000002,
GL1_CACHE_POLICY_HIT_EVICT               = 0x00000003,
} GL1_CACHE_POLICIES;

typedef enum GL1_CACHE_STORE_POLICIES {
GL1_CACHE_STORE_POLICY_BYPASS            = 0x00000000,
} GL1_CACHE_STORE_POLICIES;

typedef enum GL2A_PERF_SEL {
GL2A_PERF_SEL_NONE                       = 0x00000000,
GL2A_PERF_SEL_CYCLE                      = 0x00000001,
GL2A_PERF_SEL_BUSY                       = 0x00000002,
GL2A_PERF_SEL_REQ_GL2C0                  = 0x00000003,
GL2A_PERF_SEL_REQ_GL2C1                  = 0x00000004,
GL2A_PERF_SEL_REQ_GL2C2                  = 0x00000005,
GL2A_PERF_SEL_REQ_GL2C3                  = 0x00000006,
GL2A_PERF_SEL_REQ_GL2C4                  = 0x00000007,
GL2A_PERF_SEL_REQ_GL2C5                  = 0x00000008,
GL2A_PERF_SEL_REQ_GL2C6                  = 0x00000009,
GL2A_PERF_SEL_REQ_GL2C7                  = 0x0000000a,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0          = 0x0000000b,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1          = 0x0000000c,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2          = 0x0000000d,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3          = 0x0000000e,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4          = 0x0000000f,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5          = 0x00000010,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6          = 0x00000011,
GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7          = 0x00000012,
GL2A_PERF_SEL_REQ_BURST_GL2C0            = 0x00000013,
GL2A_PERF_SEL_REQ_BURST_GL2C1            = 0x00000014,
GL2A_PERF_SEL_REQ_BURST_GL2C2            = 0x00000015,
GL2A_PERF_SEL_REQ_BURST_GL2C3            = 0x00000016,
GL2A_PERF_SEL_REQ_BURST_GL2C4            = 0x00000017,
GL2A_PERF_SEL_REQ_BURST_GL2C5            = 0x00000018,
GL2A_PERF_SEL_REQ_BURST_GL2C6            = 0x00000019,
GL2A_PERF_SEL_REQ_BURST_GL2C7            = 0x0000001a,
GL2A_PERF_SEL_REQ_STALL_GL2C0            = 0x0000001b,
GL2A_PERF_SEL_REQ_STALL_GL2C1            = 0x0000001c,
GL2A_PERF_SEL_REQ_STALL_GL2C2            = 0x0000001d,
GL2A_PERF_SEL_REQ_STALL_GL2C3            = 0x0000001e,
GL2A_PERF_SEL_REQ_STALL_GL2C4            = 0x0000001f,
GL2A_PERF_SEL_REQ_STALL_GL2C5            = 0x00000020,
GL2A_PERF_SEL_REQ_STALL_GL2C6            = 0x00000021,
GL2A_PERF_SEL_REQ_STALL_GL2C7            = 0x00000022,
GL2A_PERF_SEL_RTN_STALL_GL2C0            = 0x00000023,
GL2A_PERF_SEL_RTN_STALL_GL2C1            = 0x00000024,
GL2A_PERF_SEL_RTN_STALL_GL2C2            = 0x00000025,
GL2A_PERF_SEL_RTN_STALL_GL2C3            = 0x00000026,
GL2A_PERF_SEL_RTN_STALL_GL2C4            = 0x00000027,
GL2A_PERF_SEL_RTN_STALL_GL2C5            = 0x00000028,
GL2A_PERF_SEL_RTN_STALL_GL2C6            = 0x00000029,
GL2A_PERF_SEL_RTN_STALL_GL2C7            = 0x0000002a,
GL2A_PERF_SEL_RTN_CLIENT0                = 0x0000002b,
GL2A_PERF_SEL_RTN_CLIENT1                = 0x0000002c,
GL2A_PERF_SEL_RTN_CLIENT2                = 0x0000002d,
GL2A_PERF_SEL_RTN_CLIENT3                = 0x0000002e,
GL2A_PERF_SEL_RTN_CLIENT4                = 0x0000002f,
GL2A_PERF_SEL_RTN_CLIENT5                = 0x00000030,
GL2A_PERF_SEL_RTN_CLIENT6                = 0x00000031,
GL2A_PERF_SEL_RTN_CLIENT7                = 0x00000032,
GL2A_PERF_SEL_RTN_CLIENT8                = 0x00000033,
GL2A_PERF_SEL_RTN_CLIENT9                = 0x00000034,
GL2A_PERF_SEL_RTN_CLIENT10               = 0x00000035,
GL2A_PERF_SEL_RTN_CLIENT11               = 0x00000036,
GL2A_PERF_SEL_RTN_CLIENT12               = 0x00000037,
GL2A_PERF_SEL_RTN_CLIENT13               = 0x00000038,
GL2A_PERF_SEL_RTN_CLIENT14               = 0x00000039,
GL2A_PERF_SEL_RTN_CLIENT15               = 0x0000003a,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0  = 0x0000003b,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1  = 0x0000003c,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2  = 0x0000003d,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3  = 0x0000003e,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4  = 0x0000003f,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5  = 0x00000040,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6  = 0x00000041,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7  = 0x00000042,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8  = 0x00000043,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9  = 0x00000044,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049,
GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a,
} GL2A_PERF_SEL;

typedef enum GL2C_PERF_SEL {
GL2C_PERF_SEL_NONE                       = 0x00000000,
GL2C_PERF_SEL_CYCLE                      = 0x00000001,
GL2C_PERF_SEL_BUSY                       = 0x00000002,
GL2C_PERF_SEL_REQ                        = 0x00000003,
GL2C_PERF_SEL_VOL_REQ                    = 0x00000004,
GL2C_PERF_SEL_HIGH_PRIORITY_REQ          = 0x00000005,
GL2C_PERF_SEL_READ                       = 0x00000006,
GL2C_PERF_SEL_WRITE                      = 0x00000007,
GL2C_PERF_SEL_ATOMIC                     = 0x00000008,
GL2C_PERF_SEL_NOP_ACK                    = 0x00000009,
GL2C_PERF_SEL_NOP_RTN0                   = 0x0000000a,
GL2C_PERF_SEL_PROBE                      = 0x0000000b,
GL2C_PERF_SEL_PROBE_ALL                  = 0x0000000c,
GL2C_PERF_SEL_INTERNAL_PROBE             = 0x0000000d,
GL2C_PERF_SEL_COMPRESSED_READ_REQ        = 0x0000000e,
GL2C_PERF_SEL_METADATA_READ_REQ          = 0x0000000f,
GL2C_PERF_SEL_CLIENT0_REQ                = 0x00000010,
GL2C_PERF_SEL_CLIENT1_REQ                = 0x00000011,
GL2C_PERF_SEL_CLIENT2_REQ                = 0x00000012,
GL2C_PERF_SEL_CLIENT3_REQ                = 0x00000013,
GL2C_PERF_SEL_CLIENT4_REQ                = 0x00000014,
GL2C_PERF_SEL_CLIENT5_REQ                = 0x00000015,
GL2C_PERF_SEL_CLIENT6_REQ                = 0x00000016,
GL2C_PERF_SEL_CLIENT7_REQ                = 0x00000017,
GL2C_PERF_SEL_C_RW_S_REQ                 = 0x00000018,
GL2C_PERF_SEL_C_RW_US_REQ                = 0x00000019,
GL2C_PERF_SEL_C_RO_S_REQ                 = 0x0000001a,
GL2C_PERF_SEL_C_RO_US_REQ                = 0x0000001b,
GL2C_PERF_SEL_UC_REQ                     = 0x0000001c,
GL2C_PERF_SEL_LRU_REQ                    = 0x0000001d,
GL2C_PERF_SEL_STREAM_REQ                 = 0x0000001e,
GL2C_PERF_SEL_BYPASS_REQ                 = 0x0000001f,
GL2C_PERF_SEL_NOA_REQ                    = 0x00000020,
GL2C_PERF_SEL_SHARED_REQ                 = 0x00000021,
GL2C_PERF_SEL_HIT                        = 0x00000022,
GL2C_PERF_SEL_MISS                       = 0x00000023,
GL2C_PERF_SEL_FULL_HIT                   = 0x00000024,
GL2C_PERF_SEL_PARTIAL_32B_HIT            = 0x00000025,
GL2C_PERF_SEL_PARTIAL_64B_HIT            = 0x00000026,
GL2C_PERF_SEL_PARTIAL_96B_HIT            = 0x00000027,
GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT       = 0x00000028,
GL2C_PERF_SEL_FULLY_WRITTEN_HIT          = 0x00000029,
GL2C_PERF_SEL_UNCACHED_WRITE             = 0x0000002a,
GL2C_PERF_SEL_WRITEBACK                  = 0x0000002b,
GL2C_PERF_SEL_NORMAL_WRITEBACK           = 0x0000002c,
GL2C_PERF_SEL_EVICT                      = 0x0000002d,
GL2C_PERF_SEL_NORMAL_EVICT               = 0x0000002e,
GL2C_PERF_SEL_PROBE_EVICT                = 0x0000002f,
GL2C_PERF_SEL_REQ_TO_MISS_QUEUE          = 0x00000030,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO   = 0x00000031,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP      = 0x00000032,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0   = 0x00000033,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1   = 0x00000034,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2   = 0x00000035,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3   = 0x00000036,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4   = 0x00000037,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5   = 0x00000038,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6   = 0x00000039,
GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7   = 0x0000003a,
GL2C_PERF_SEL_READ_32_REQ                = 0x0000003b,
GL2C_PERF_SEL_READ_64_REQ                = 0x0000003c,
GL2C_PERF_SEL_READ_128_REQ               = 0x0000003d,
GL2C_PERF_SEL_WRITE_32_REQ               = 0x0000003e,
GL2C_PERF_SEL_WRITE_64_REQ               = 0x0000003f,
GL2C_PERF_SEL_COMPRESSED_READ_0_REQ      = 0x00000040,
GL2C_PERF_SEL_COMPRESSED_READ_32_REQ     = 0x00000041,
GL2C_PERF_SEL_COMPRESSED_READ_64_REQ     = 0x00000042,
GL2C_PERF_SEL_COMPRESSED_READ_96_REQ     = 0x00000043,
GL2C_PERF_SEL_COMPRESSED_READ_128_REQ    = 0x00000044,
GL2C_PERF_SEL_MC_WRREQ                   = 0x00000045,
GL2C_PERF_SEL_EA_WRREQ_64B               = 0x00000046,
GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND     = 0x00000047,
GL2C_PERF_SEL_EA_WR_UNCACHED_32B         = 0x00000048,
GL2C_PERF_SEL_MC_WRREQ_STALL             = 0x00000049,
GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL   = 0x0000004a,
GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL  = 0x0000004b,
GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000004c,
GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL   = 0x0000004d,
GL2C_PERF_SEL_MC_WRREQ_LEVEL             = 0x0000004e,
GL2C_PERF_SEL_EA_ATOMIC                  = 0x0000004f,
GL2C_PERF_SEL_EA_ATOMIC_LEVEL            = 0x00000050,
GL2C_PERF_SEL_MC_RDREQ                   = 0x00000051,
GL2C_PERF_SEL_EA_RDREQ_SPLIT             = 0x00000052,
GL2C_PERF_SEL_EA_RDREQ_32B               = 0x00000053,
GL2C_PERF_SEL_EA_RDREQ_64B               = 0x00000054,
GL2C_PERF_SEL_EA_RDREQ_96B               = 0x00000055,
GL2C_PERF_SEL_EA_RDREQ_128B              = 0x00000056,
GL2C_PERF_SEL_EA_RD_UNCACHED_32B         = 0x00000057,
GL2C_PERF_SEL_EA_RD_MDC_32B              = 0x00000058,
GL2C_PERF_SEL_EA_RD_COMPRESSED_32B       = 0x00000059,
GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL   = 0x0000005a,
GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL  = 0x0000005b,
GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000005c,
GL2C_PERF_SEL_MC_RDREQ_LEVEL             = 0x0000005d,
GL2C_PERF_SEL_EA_RDREQ_DRAM              = 0x0000005e,
GL2C_PERF_SEL_EA_WRREQ_DRAM              = 0x0000005f,
GL2C_PERF_SEL_EA_RDREQ_DRAM_32B          = 0x00000060,
GL2C_PERF_SEL_EA_WRREQ_DRAM_32B          = 0x00000061,
GL2C_PERF_SEL_ONION_READ                 = 0x00000062,
GL2C_PERF_SEL_ONION_WRITE                = 0x00000063,
GL2C_PERF_SEL_IO_READ                    = 0x00000064,
GL2C_PERF_SEL_IO_WRITE                   = 0x00000065,
GL2C_PERF_SEL_GARLIC_READ                = 0x00000066,
GL2C_PERF_SEL_GARLIC_WRITE               = 0x00000067,
GL2C_PERF_SEL_LATENCY_FIFO_FULL          = 0x00000068,
GL2C_PERF_SEL_SRC_FIFO_FULL              = 0x00000069,
GL2C_PERF_SEL_TAG_STALL                  = 0x0000006a,
GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000006b,
GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000006c,
GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000006d,
GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000006e,
GL2C_PERF_SEL_TAG_PROBE_STALL            = 0x0000006f,
GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL     = 0x00000070,
GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL  = 0x00000071,
GL2C_PERF_SEL_TAG_READ_DST_STALL         = 0x00000072,
GL2C_PERF_SEL_READ_RETURN_TIMEOUT        = 0x00000073,
GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT     = 0x00000074,
GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE    = 0x00000075,
GL2C_PERF_SEL_BUBBLE                     = 0x00000076,
GL2C_PERF_SEL_IB_REQ                     = 0x00000077,
GL2C_PERF_SEL_IB_STALL                   = 0x00000078,
GL2C_PERF_SEL_IB_TAG_STALL               = 0x00000079,
GL2C_PERF_SEL_IB_CM_STALL                = 0x0000007a,
GL2C_PERF_SEL_RETURN_ACK                 = 0x0000007b,
GL2C_PERF_SEL_RETURN_DATA                = 0x0000007c,
GL2C_PERF_SEL_EA_RDRET_NACK              = 0x0000007d,
GL2C_PERF_SEL_EA_WRRET_NACK              = 0x0000007e,
GL2C_PERF_SEL_GL2A_LEVEL                 = 0x0000007f,
GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000080,
GL2C_PERF_SEL_PROBE_FILTER_DISABLED      = 0x00000081,
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START  = 0x00000082,
GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000083,
GL2C_PERF_SEL_GCR_INV                    = 0x00000084,
GL2C_PERF_SEL_GCR_WB                     = 0x00000085,
GL2C_PERF_SEL_GCR_DISCARD                = 0x00000086,
GL2C_PERF_SEL_GCR_RANGE                  = 0x00000087,
GL2C_PERF_SEL_GCR_ALL                    = 0x00000088,
GL2C_PERF_SEL_GCR_VOL                    = 0x00000089,
GL2C_PERF_SEL_GCR_UNSHARED               = 0x0000008a,
GL2C_PERF_SEL_GCR_MDC_INV                = 0x0000008b,
GL2C_PERF_SEL_GCR_GL2_INV_ALL            = 0x0000008c,
GL2C_PERF_SEL_GCR_GL2_WB_ALL             = 0x0000008d,
GL2C_PERF_SEL_GCR_MDC_INV_ALL            = 0x0000008e,
GL2C_PERF_SEL_GCR_GL2_INV_RANGE          = 0x0000008f,
GL2C_PERF_SEL_GCR_GL2_WB_RANGE           = 0x00000090,
GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE       = 0x00000091,
GL2C_PERF_SEL_GCR_MDC_INV_RANGE          = 0x00000092,
GL2C_PERF_SEL_ALL_GCR_INV_EVICT          = 0x00000093,
GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT      = 0x00000094,
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE    = 0x00000095,
GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x00000096,
GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK       = 0x00000097,
GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE        = 0x00000098,
GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT        = 0x00000099,
GL2C_PERF_SEL_GCR_INVL2_VOL_START        = 0x0000009a,
GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE         = 0x0000009b,
GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT         = 0x0000009c,
GL2C_PERF_SEL_GCR_WBL2_VOL_START         = 0x0000009d,
GL2C_PERF_SEL_GCR_WBINVL2_CYCLE          = 0x0000009e,
GL2C_PERF_SEL_GCR_WBINVL2_EVICT          = 0x0000009f,
GL2C_PERF_SEL_GCR_WBINVL2_START          = 0x000000a0,
GL2C_PERF_SEL_MDC_INV_METADATA           = 0x000000a1,
GL2C_PERF_SEL_MDC_REQ                    = 0x000000a2,
GL2C_PERF_SEL_MDC_LEVEL                  = 0x000000a3,
GL2C_PERF_SEL_MDC_TAG_HIT                = 0x000000a4,
GL2C_PERF_SEL_MDC_SECTOR_HIT             = 0x000000a5,
GL2C_PERF_SEL_MDC_SECTOR_MISS            = 0x000000a6,
GL2C_PERF_SEL_MDC_TAG_STALL              = 0x000000a7,
GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000a8,
GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000a9,
GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000aa,
GL2C_PERF_SEL_CM_CHANNEL0_REQ            = 0x000000ab,
GL2C_PERF_SEL_CM_CHANNEL1_REQ            = 0x000000ac,
GL2C_PERF_SEL_CM_CHANNEL2_REQ            = 0x000000ad,
GL2C_PERF_SEL_CM_CHANNEL3_REQ            = 0x000000ae,
GL2C_PERF_SEL_CM_CHANNEL4_REQ            = 0x000000af,
GL2C_PERF_SEL_CM_CHANNEL5_REQ            = 0x000000b0,
GL2C_PERF_SEL_CM_CHANNEL6_REQ            = 0x000000b1,
GL2C_PERF_SEL_CM_CHANNEL7_REQ            = 0x000000b2,
GL2C_PERF_SEL_CM_CHANNEL8_REQ            = 0x000000b3,
GL2C_PERF_SEL_CM_CHANNEL9_REQ            = 0x000000b4,
GL2C_PERF_SEL_CM_CHANNEL10_REQ           = 0x000000b5,
GL2C_PERF_SEL_CM_CHANNEL11_REQ           = 0x000000b6,
GL2C_PERF_SEL_CM_CHANNEL12_REQ           = 0x000000b7,
GL2C_PERF_SEL_CM_CHANNEL13_REQ           = 0x000000b8,
GL2C_PERF_SEL_CM_CHANNEL14_REQ           = 0x000000b9,
GL2C_PERF_SEL_CM_CHANNEL15_REQ           = 0x000000ba,
GL2C_PERF_SEL_CM_CHANNEL16_REQ           = 0x000000bb,
GL2C_PERF_SEL_CM_CHANNEL17_REQ           = 0x000000bc,
GL2C_PERF_SEL_CM_CHANNEL18_REQ           = 0x000000bd,
GL2C_PERF_SEL_CM_CHANNEL19_REQ           = 0x000000be,
GL2C_PERF_SEL_CM_CHANNEL20_REQ           = 0x000000bf,
GL2C_PERF_SEL_CM_CHANNEL21_REQ           = 0x000000c0,
GL2C_PERF_SEL_CM_CHANNEL22_REQ           = 0x000000c1,
GL2C_PERF_SEL_CM_CHANNEL23_REQ           = 0x000000c2,
GL2C_PERF_SEL_CM_CHANNEL24_REQ           = 0x000000c3,
GL2C_PERF_SEL_CM_CHANNEL25_REQ           = 0x000000c4,
GL2C_PERF_SEL_CM_CHANNEL26_REQ           = 0x000000c5,
GL2C_PERF_SEL_CM_CHANNEL27_REQ           = 0x000000c6,
GL2C_PERF_SEL_CM_CHANNEL28_REQ           = 0x000000c7,
GL2C_PERF_SEL_CM_CHANNEL29_REQ           = 0x000000c8,
GL2C_PERF_SEL_CM_CHANNEL30_REQ           = 0x000000c9,
GL2C_PERF_SEL_CM_CHANNEL31_REQ           = 0x000000ca,
GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ   = 0x000000cb,
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000cc,
GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000cd,
GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ    = 0x000000ce,
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ  = 0x000000cf,
GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ  = 0x000000d0,
GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ  = 0x000000d1,
GL2C_PERF_SEL_CM_COMP_READ_REQ           = 0x000000d2,
GL2C_PERF_SEL_CM_READ_BACK_REQ           = 0x000000d3,
GL2C_PERF_SEL_CM_METADATA_WR_REQ         = 0x000000d4,
GL2C_PERF_SEL_CM_WR_ACK_REQ              = 0x000000d5,
GL2C_PERF_SEL_CM_NO_ACK_REQ              = 0x000000d6,
GL2C_PERF_SEL_CM_NOOP_REQ                = 0x000000d7,
GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ       = 0x000000d8,
GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ      = 0x000000d9,
GL2C_PERF_SEL_CM_COMP_STENCIL_REQ        = 0x000000da,
GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ        = 0x000000db,
GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ        = 0x000000dc,
GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ        = 0x000000dd,
GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ        = 0x000000de,
GL2C_PERF_SEL_CM_FULL_WRITE_REQ          = 0x000000df,
GL2C_PERF_SEL_CM_RVF_FULL                = 0x000000e0,
GL2C_PERF_SEL_CM_SDR_FULL                = 0x000000e1,
GL2C_PERF_SEL_CM_MERGE_BUF_FULL          = 0x000000e2,
GL2C_PERF_SEL_CM_DCC_STALL               = 0x000000e3,
} GL2C_PERF_SEL;

typedef enum GL2_CACHE_POLICIES {
GL2_CACHE_POLICY_LRU                     = 0x00000000,
GL2_CACHE_POLICY_STREAM                  = 0x00000001,
GL2_CACHE_POLICY_NOA                     = 0x00000002,
GL2_CACHE_POLICY_BYPASS                  = 0x00000003,
} GL2_CACHE_POLICIES;

typedef enum GL2_EA_CID {
GL2_EA_CID_CLIENT                        = 0x00000000,
GL2_EA_CID_SDMA                          = 0x00000001,
GL2_EA_CID_RLC                           = 0x00000002,
GL2_EA_CID_ACV                           = 0x00000003,
GL2_EA_CID_CP                            = 0x00000004,
GL2_EA_CID_CPDMA                         = 0x00000005,
GL2_EA_CID_UTCL2                         = 0x00000006,
GL2_EA_CID_RT                            = 0x00000007,
GL2_EA_CID_FMASK                         = 0x00000008,
GL2_EA_CID_DCC                           = 0x00000009,
GL2_EA_CID_Z_STENCIL                     = 0x0000000a,
GL2_EA_CID_ZPCPSD                        = 0x0000000b,
GL2_EA_CID_HTILE                         = 0x0000000c,
GL2_EA_CID_TCPMETA                       = 0x0000000f,
} GL2_EA_CID;

typedef enum GL2_NACKS {
GL2_NACK_NO_FAULT                        = 0x00000000,
GL2_NACK_PAGE_FAULT                      = 0x00000001,
GL2_NACK_PROTECTION_FAULT                = 0x00000002,
GL2_NACK_DATA_ERROR                      = 0x00000003,
} GL2_NACKS;

typedef enum GL2_OP {
GL2_OP_READ                              = 0x00000000,
GL2_OP_ATOMIC_FCMPSWAP_RTN_32            = 0x00000001,
GL2_OP_ATOMIC_FMIN_RTN_32                = 0x00000002,
GL2_OP_ATOMIC_FMAX_RTN_32                = 0x00000003,
GL2_OP_ATOMIC_SWAP_RTN_32                = 0x00000007,
GL2_OP_ATOMIC_CMPSWAP_RTN_32             = 0x00000008,
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32   = 0x0000000a,
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32   = 0x0000000b,
GL2_OP_PROBE_FILTER                      = 0x0000000c,
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
GL2_OP_ATOMIC_ADD_RTN_32                 = 0x0000000f,
GL2_OP_ATOMIC_SUB_RTN_32                 = 0x00000010,
GL2_OP_ATOMIC_SMIN_RTN_32                = 0x00000011,
GL2_OP_ATOMIC_UMIN_RTN_32                = 0x00000012,
GL2_OP_ATOMIC_SMAX_RTN_32                = 0x00000013,
GL2_OP_ATOMIC_UMAX_RTN_32                = 0x00000014,
GL2_OP_ATOMIC_AND_RTN_32                 = 0x00000015,
GL2_OP_ATOMIC_OR_RTN_32                  = 0x00000016,
GL2_OP_ATOMIC_XOR_RTN_32                 = 0x00000017,
GL2_OP_ATOMIC_INC_RTN_32                 = 0x00000018,
GL2_OP_ATOMIC_DEC_RTN_32                 = 0x00000019,
GL2_OP_WRITE                             = 0x00000020,
GL2_OP_ATOMIC_FCMPSWAP_RTN_64            = 0x00000021,
GL2_OP_ATOMIC_FMIN_RTN_64                = 0x00000022,
GL2_OP_ATOMIC_FMAX_RTN_64                = 0x00000023,
GL2_OP_ATOMIC_SWAP_RTN_64                = 0x00000027,
GL2_OP_ATOMIC_CMPSWAP_RTN_64             = 0x00000028,
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64   = 0x0000002a,
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64   = 0x0000002b,
GL2_OP_ATOMIC_ADD_RTN_64                 = 0x0000002f,
GL2_OP_ATOMIC_SUB_RTN_64                 = 0x00000030,
GL2_OP_ATOMIC_SMIN_RTN_64                = 0x00000031,
GL2_OP_ATOMIC_UMIN_RTN_64                = 0x00000032,
GL2_OP_ATOMIC_SMAX_RTN_64                = 0x00000033,
GL2_OP_ATOMIC_UMAX_RTN_64                = 0x00000034,
GL2_OP_ATOMIC_AND_RTN_64                 = 0x00000035,
GL2_OP_ATOMIC_OR_RTN_64                  = 0x00000036,
GL2_OP_ATOMIC_XOR_RTN_64                 = 0x00000037,
GL2_OP_ATOMIC_INC_RTN_64                 = 0x00000038,
GL2_OP_ATOMIC_DEC_RTN_64                 = 0x00000039,
GL2_OP_GL1_INV                           = 0x00000040,
GL2_OP_ATOMIC_FCMPSWAP_32                = 0x00000041,
GL2_OP_ATOMIC_FMIN_32                    = 0x00000042,
GL2_OP_ATOMIC_FMAX_32                    = 0x00000043,
GL2_OP_ATOMIC_SWAP_32                    = 0x00000047,
GL2_OP_ATOMIC_CMPSWAP_32                 = 0x00000048,
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32   = 0x00000049,
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32       = 0x0000004a,
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32       = 0x0000004b,
GL2_OP_ATOMIC_ADD_32                     = 0x0000004f,
GL2_OP_ATOMIC_SUB_32                     = 0x00000050,
GL2_OP_ATOMIC_SMIN_32                    = 0x00000051,
GL2_OP_ATOMIC_UMIN_32                    = 0x00000052,
GL2_OP_ATOMIC_SMAX_32                    = 0x00000053,
GL2_OP_ATOMIC_UMAX_32                    = 0x00000054,
GL2_OP_ATOMIC_AND_32                     = 0x00000055,
GL2_OP_ATOMIC_OR_32                      = 0x00000056,
GL2_OP_ATOMIC_XOR_32                     = 0x00000057,
GL2_OP_ATOMIC_INC_32                     = 0x00000058,
GL2_OP_ATOMIC_DEC_32                     = 0x00000059,
GL2_OP_NOP_RTN0                          = 0x0000005b,
GL2_OP_ATOMIC_FCMPSWAP_64                = 0x00000061,
GL2_OP_ATOMIC_FMIN_64                    = 0x00000062,
GL2_OP_ATOMIC_FMAX_64                    = 0x00000063,
GL2_OP_ATOMIC_SWAP_64                    = 0x00000067,
GL2_OP_ATOMIC_CMPSWAP_64                 = 0x00000068,
GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64   = 0x00000069,
GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64       = 0x0000006a,
GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64       = 0x0000006b,
GL2_OP_ATOMIC_ADD_64                     = 0x0000006f,
GL2_OP_ATOMIC_SUB_64                     = 0x00000070,
GL2_OP_ATOMIC_SMIN_64                    = 0x00000071,
GL2_OP_ATOMIC_UMIN_64                    = 0x00000072,
GL2_OP_ATOMIC_SMAX_64                    = 0x00000073,
GL2_OP_ATOMIC_UMAX_64                    = 0x00000074,
GL2_OP_ATOMIC_AND_64                     = 0x00000075,
GL2_OP_ATOMIC_OR_64                      = 0x00000076,
GL2_OP_ATOMIC_XOR_64                     = 0x00000077,
GL2_OP_ATOMIC_INC_64                     = 0x00000078,
GL2_OP_ATOMIC_DEC_64                     = 0x00000079,
GL2_OP_NOP_ACK                           = 0x0000007b,
} GL2_OP;

typedef enum GL2_OP_MASKS {
GL2_OP_MASK_FLUSH_DENROM                 = 0x00000008,
GL2_OP_MASK_64                           = 0x00000020,
GL2_OP_MASK_NO_RTN                       = 0x00000040,
} GL2_OP_MASKS;

typedef enum IH_CLIENT_TYPE {
IH_GFX_VMID_CLIENT                       = 0x00000000,
IH_MM_VMID_CLIENT                        = 0x00000001,
IH_MULTI_VMID_CLIENT                     = 0x00000002,
IH_CLIENT_TYPE_RESERVED                  = 0x00000003,
} IH_CLIENT_TYPE;

typedef enum IH_INTERFACE_TYPE {
IH_LEGACY_INTERFACE                      = 0x00000000,
IH_REGISTER_WRITE_INTERFACE              = 0x00000001,
} IH_INTERFACE_TYPE;

typedef enum IH_RING_ID {
IH_RING_ID_INTERRUPT                     = 0x00000000,
IH_RING_ID_REQUEST                       = 0x00000001,
IH_RING_ID_TRANSLATION                   = 0x00000002,
IH_RING_ID_RESERVED                      = 0x00000003,
} IH_RING_ID;

typedef enum IH_VF_RB_SELECT {
IH_VF_RB_SELECT_CLIENT_FCN_ID            = 0x00000000,
IH_VF_RB_SELECT_IH_FCN_ID                = 0x00000001,
IH_VF_RB_SELECT_PF                       = 0x00000002,
IH_VF_RB_SELECT_RESERVED                 = 0x00000003,
} IH_VF_RB_SELECT;

typedef enum IMG_FMT {
IMG_FMT_INVALID                          = 0x00000000,
IMG_FMT_8_UNORM                          = 0x00000001,
IMG_FMT_8_SNORM                          = 0x00000002,
IMG_FMT_8_USCALED                        = 0x00000003,
IMG_FMT_8_SSCALED                        = 0x00000004,
IMG_FMT_8_UINT                           = 0x00000005,
IMG_FMT_8_SINT                           = 0x00000006,
IMG_FMT_16_UNORM                         = 0x00000007,
IMG_FMT_16_SNORM                         = 0x00000008,
IMG_FMT_16_USCALED                       = 0x00000009,
IMG_FMT_16_SSCALED                       = 0x0000000a,
IMG_FMT_16_UINT                          = 0x0000000b,
IMG_FMT_16_SINT                          = 0x0000000c,
IMG_FMT_16_FLOAT                         = 0x0000000d,
IMG_FMT_8_8_UNORM                        = 0x0000000e,
IMG_FMT_8_8_SNORM                        = 0x0000000f,
IMG_FMT_8_8_USCALED                      = 0x00000010,
IMG_FMT_8_8_SSCALED                      = 0x00000011,
IMG_FMT_8_8_UINT                         = 0x00000012,
IMG_FMT_8_8_SINT                         = 0x00000013,
IMG_FMT_32_UINT                          = 0x00000014,
IMG_FMT_32_SINT                          = 0x00000015,
IMG_FMT_32_FLOAT                         = 0x00000016,
IMG_FMT_16_16_UNORM                      = 0x00000017,
IMG_FMT_16_16_SNORM                      = 0x00000018,
IMG_FMT_16_16_USCALED                    = 0x00000019,
IMG_FMT_16_16_SSCALED                    = 0x0000001a,
IMG_FMT_16_16_UINT                       = 0x0000001b,
IMG_FMT_16_16_SINT                       = 0x0000001c,
IMG_FMT_16_16_FLOAT                      = 0x0000001d,
IMG_FMT_10_11_11_UNORM                   = 0x0000001e,
IMG_FMT_10_11_11_SNORM                   = 0x0000001f,
IMG_FMT_10_11_11_USCALED                 = 0x00000020,
IMG_FMT_10_11_11_SSCALED                 = 0x00000021,
IMG_FMT_10_11_11_UINT                    = 0x00000022,
IMG_FMT_10_11_11_SINT                    = 0x00000023,
IMG_FMT_10_11_11_FLOAT                   = 0x00000024,
IMG_FMT_11_11_10_UNORM                   = 0x00000025,
IMG_FMT_11_11_10_SNORM                   = 0x00000026,
IMG_FMT_11_11_10_USCALED                 = 0x00000027,
IMG_FMT_11_11_10_SSCALED                 = 0x00000028,
IMG_FMT_11_11_10_UINT                    = 0x00000029,
IMG_FMT_11_11_10_SINT                    = 0x0000002a,
IMG_FMT_11_11_10_FLOAT                   = 0x0000002b,
IMG_FMT_10_10_10_2_UNORM                 = 0x0000002c,
IMG_FMT_10_10_10_2_SNORM                 = 0x0000002d,
IMG_FMT_10_10_10_2_USCALED               = 0x0000002e,
IMG_FMT_10_10_10_2_SSCALED               = 0x0000002f,
IMG_FMT_10_10_10_2_UINT                  = 0x00000030,
IMG_FMT_10_10_10_2_SINT                  = 0x00000031,
IMG_FMT_2_10_10_10_UNORM                 = 0x00000032,
IMG_FMT_2_10_10_10_SNORM                 = 0x00000033,
IMG_FMT_2_10_10_10_USCALED               = 0x00000034,
IMG_FMT_2_10_10_10_SSCALED               = 0x00000035,
IMG_FMT_2_10_10_10_UINT                  = 0x00000036,
IMG_FMT_2_10_10_10_SINT                  = 0x00000037,
IMG_FMT_8_8_8_8_UNORM                    = 0x00000038,
IMG_FMT_8_8_8_8_SNORM                    = 0x00000039,
IMG_FMT_8_8_8_8_USCALED                  = 0x0000003a,
IMG_FMT_8_8_8_8_SSCALED                  = 0x0000003b,
IMG_FMT_8_8_8_8_UINT                     = 0x0000003c,
IMG_FMT_8_8_8_8_SINT                     = 0x0000003d,
IMG_FMT_32_32_UINT                       = 0x0000003e,
IMG_FMT_32_32_SINT                       = 0x0000003f,
IMG_FMT_32_32_FLOAT                      = 0x00000040,
IMG_FMT_16_16_16_16_UNORM                = 0x00000041,
IMG_FMT_16_16_16_16_SNORM                = 0x00000042,
IMG_FMT_16_16_16_16_USCALED              = 0x00000043,
IMG_FMT_16_16_16_16_SSCALED              = 0x00000044,
IMG_FMT_16_16_16_16_UINT                 = 0x00000045,
IMG_FMT_16_16_16_16_SINT                 = 0x00000046,
IMG_FMT_16_16_16_16_FLOAT                = 0x00000047,
IMG_FMT_32_32_32_UINT                    = 0x00000048,
IMG_FMT_32_32_32_SINT                    = 0x00000049,
IMG_FMT_32_32_32_FLOAT                   = 0x0000004a,
IMG_FMT_32_32_32_32_UINT                 = 0x0000004b,
IMG_FMT_32_32_32_32_SINT                 = 0x0000004c,
IMG_FMT_32_32_32_32_FLOAT                = 0x0000004d,
IMG_FMT_RESERVED_78                      = 0x0000004e,
IMG_FMT_RESERVED_79                      = 0x0000004f,
IMG_FMT_RESERVED_80                      = 0x00000050,
IMG_FMT_RESERVED_81                      = 0x00000051,
IMG_FMT_RESERVED_82                      = 0x00000052,
IMG_FMT_RESERVED_83                      = 0x00000053,
IMG_FMT_RESERVED_84                      = 0x00000054,
IMG_FMT_RESERVED_85                      = 0x00000055,
IMG_FMT_RESERVED_86                      = 0x00000056,
IMG_FMT_RESERVED_87                      = 0x00000057,
IMG_FMT_RESERVED_88                      = 0x00000058,
IMG_FMT_RESERVED_89                      = 0x00000059,
IMG_FMT_RESERVED_90                      = 0x0000005a,
IMG_FMT_RESERVED_91                      = 0x0000005b,
IMG_FMT_RESERVED_92                      = 0x0000005c,
IMG_FMT_RESERVED_93                      = 0x0000005d,
IMG_FMT_RESERVED_94                      = 0x0000005e,
IMG_FMT_RESERVED_95                      = 0x0000005f,
IMG_FMT_RESERVED_96                      = 0x00000060,
IMG_FMT_RESERVED_97                      = 0x00000061,
IMG_FMT_RESERVED_98                      = 0x00000062,
IMG_FMT_RESERVED_99                      = 0x00000063,
IMG_FMT_RESERVED_100                     = 0x00000064,
IMG_FMT_RESERVED_101                     = 0x00000065,
IMG_FMT_RESERVED_102                     = 0x00000066,
IMG_FMT_RESERVED_103                     = 0x00000067,
IMG_FMT_RESERVED_104                     = 0x00000068,
IMG_FMT_RESERVED_105                     = 0x00000069,
IMG_FMT_RESERVED_106                     = 0x0000006a,
IMG_FMT_RESERVED_107                     = 0x0000006b,
IMG_FMT_RESERVED_108                     = 0x0000006c,
IMG_FMT_RESERVED_109                     = 0x0000006d,
IMG_FMT_RESERVED_110                     = 0x0000006e,
IMG_FMT_RESERVED_111                     = 0x0000006f,
IMG_FMT_RESERVED_112                     = 0x00000070,
IMG_FMT_RESERVED_113                     = 0x00000071,
IMG_FMT_RESERVED_114                     = 0x00000072,
IMG_FMT_RESERVED_115                     = 0x00000073,
IMG_FMT_RESERVED_116                     = 0x00000074,
IMG_FMT_RESERVED_117                     = 0x00000075,
IMG_FMT_RESERVED_118                     = 0x00000076,
IMG_FMT_RESERVED_119                     = 0x00000077,
IMG_FMT_RESERVED_120                     = 0x00000078,
IMG_FMT_RESERVED_121                     = 0x00000079,
IMG_FMT_RESERVED_122                     = 0x0000007a,
IMG_FMT_RESERVED_123                     = 0x0000007b,
IMG_FMT_RESERVED_124                     = 0x0000007c,
IMG_FMT_RESERVED_125                     = 0x0000007d,
IMG_FMT_RESERVED_126                     = 0x0000007e,
IMG_FMT_RESERVED_127                     = 0x0000007f,
IMG_FMT_8_SRGB                           = 0x00000080,
IMG_FMT_8_8_SRGB                         = 0x00000081,
IMG_FMT_8_8_8_8_SRGB                     = 0x00000082,
IMG_FMT_6E4_FLOAT                        = 0x00000083,
IMG_FMT_5_9_9_9_FLOAT                    = 0x00000084,
IMG_FMT_5_6_5_UNORM                      = 0x00000085,
IMG_FMT_1_5_5_5_UNORM                    = 0x00000086,
IMG_FMT_5_5_5_1_UNORM                    = 0x00000087,
IMG_FMT_4_4_4_4_UNORM                    = 0x00000088,
IMG_FMT_4_4_UNORM                        = 0x00000089,
IMG_FMT_1_UNORM                          = 0x0000008a,
IMG_FMT_1_REVERSED_UNORM                 = 0x0000008b,
IMG_FMT_32_FLOAT_CLAMP                   = 0x0000008c,
IMG_FMT_8_24_UNORM                       = 0x0000008d,
IMG_FMT_8_24_UINT                        = 0x0000008e,
IMG_FMT_24_8_UNORM                       = 0x0000008f,
IMG_FMT_24_8_UINT                        = 0x00000090,
IMG_FMT_X24_8_32_UINT                    = 0x00000091,
IMG_FMT_X24_8_32_FLOAT                   = 0x00000092,
IMG_FMT_GB_GR_UNORM                      = 0x00000093,
IMG_FMT_GB_GR_SNORM                      = 0x00000094,
IMG_FMT_GB_GR_UINT                       = 0x00000095,
IMG_FMT_GB_GR_SRGB                       = 0x00000096,
IMG_FMT_BG_RG_UNORM                      = 0x00000097,
IMG_FMT_BG_RG_SNORM                      = 0x00000098,
IMG_FMT_BG_RG_UINT                       = 0x00000099,
IMG_FMT_BG_RG_SRGB                       = 0x0000009a,
IMG_FMT_RESERVED_155                     = 0x0000009b,
IMG_FMT_FMASK8_S2_F1                     = 0x0000009c,
IMG_FMT_FMASK8_S4_F1                     = 0x0000009d,
IMG_FMT_FMASK8_S8_F1                     = 0x0000009e,
IMG_FMT_FMASK8_S2_F2                     = 0x0000009f,
IMG_FMT_FMASK8_S4_F2                     = 0x000000a0,
IMG_FMT_FMASK8_S4_F4                     = 0x000000a1,
IMG_FMT_FMASK16_S16_F1                   = 0x000000a2,
IMG_FMT_FMASK16_S8_F2                    = 0x000000a3,
IMG_FMT_FMASK32_S16_F2                   = 0x000000a4,
IMG_FMT_FMASK32_S8_F4                    = 0x000000a5,
IMG_FMT_FMASK32_S8_F8                    = 0x000000a6,
IMG_FMT_FMASK64_S16_F4                   = 0x000000a7,
IMG_FMT_FMASK64_S16_F8                   = 0x000000a8,
IMG_FMT_BC1_UNORM                        = 0x000000a9,
IMG_FMT_BC1_SRGB                         = 0x000000aa,
IMG_FMT_BC2_UNORM                        = 0x000000ab,
IMG_FMT_BC2_SRGB                         = 0x000000ac,
IMG_FMT_BC3_UNORM                        = 0x000000ad,
IMG_FMT_BC3_SRGB                         = 0x000000ae,
IMG_FMT_BC4_UNORM                        = 0x000000af,
IMG_FMT_BC4_SNORM                        = 0x000000b0,
IMG_FMT_BC5_UNORM                        = 0x000000b1,
IMG_FMT_BC5_SNORM                        = 0x000000b2,
IMG_FMT_BC6_UFLOAT                       = 0x000000b3,
IMG_FMT_BC6_SFLOAT                       = 0x000000b4,
IMG_FMT_BC7_UNORM                        = 0x000000b5,
IMG_FMT_BC7_SRGB                         = 0x000000b6,
IMG_FMT_ETC2_RGB_UNORM                   = 0x000000b7,
IMG_FMT_ETC2_RGB_SRGB                    = 0x000000b8,
IMG_FMT_ETC2_RGBA_UNORM                  = 0x000000b9,
IMG_FMT_ETC2_RGBA_SRGB                   = 0x000000ba,
IMG_FMT_ETC2_R_UNORM                     = 0x000000bb,
IMG_FMT_ETC2_R_SNORM                     = 0x000000bc,
IMG_FMT_ETC2_RG_UNORM                    = 0x000000bd,
IMG_FMT_ETC2_RG_SNORM                    = 0x000000be,
IMG_FMT_ETC2_RGBA1_UNORM                 = 0x000000bf,
IMG_FMT_ETC2_RGBA1_SRGB                  = 0x000000c0,
IMG_FMT_ASTC_2D_LDR_4X4                  = 0x000000c1,
IMG_FMT_ASTC_2D_LDR_5X4                  = 0x000000c2,
IMG_FMT_ASTC_2D_LDR_5X5                  = 0x000000c3,
IMG_FMT_ASTC_2D_LDR_6X5                  = 0x000000c4,
IMG_FMT_ASTC_2D_LDR_6X6                  = 0x000000c5,
IMG_FMT_ASTC_2D_LDR_8X5                  = 0x000000c6,
IMG_FMT_ASTC_2D_LDR_8X6                  = 0x000000c7,
IMG_FMT_ASTC_2D_LDR_8X8                  = 0x000000c8,
IMG_FMT_ASTC_2D_LDR_10X5                 = 0x000000c9,
IMG_FMT_ASTC_2D_LDR_10X6                 = 0x000000ca,
IMG_FMT_ASTC_2D_LDR_10X8                 = 0x000000cb,
IMG_FMT_ASTC_2D_LDR_10X10                = 0x000000cc,
IMG_FMT_ASTC_2D_LDR_12X10                = 0x000000cd,
IMG_FMT_ASTC_2D_LDR_12X12                = 0x000000ce,
IMG_FMT_ASTC_2D_HDR_4X4                  = 0x000000cf,
IMG_FMT_ASTC_2D_HDR_5X4                  = 0x000000d0,
IMG_FMT_ASTC_2D_HDR_5X5                  = 0x000000d1,
IMG_FMT_ASTC_2D_HDR_6X5                  = 0x000000d2,
IMG_FMT_ASTC_2D_HDR_6X6                  = 0x000000d3,
IMG_FMT_ASTC_2D_HDR_8X5                  = 0x000000d4,
IMG_FMT_ASTC_2D_HDR_8X6                  = 0x000000d5,
IMG_FMT_ASTC_2D_HDR_8X8                  = 0x000000d6,
IMG_FMT_ASTC_2D_HDR_10X5                 = 0x000000d7,
IMG_FMT_ASTC_2D_HDR_10X6                 = 0x000000d8,
IMG_FMT_ASTC_2D_HDR_10X8                 = 0x000000d9,
IMG_FMT_ASTC_2D_HDR_10X10                = 0x000000da,
IMG_FMT_ASTC_2D_HDR_12X10                = 0x000000db,
IMG_FMT_ASTC_2D_HDR_12X12                = 0x000000dc,
IMG_FMT_ASTC_2D_LDR_SRGB_4X4             = 0x000000dd,
IMG_FMT_ASTC_2D_LDR_SRGB_5X4             = 0x000000de,
IMG_FMT_ASTC_2D_LDR_SRGB_5X5             = 0x000000df,
IMG_FMT_ASTC_2D_LDR_SRGB_6X5             = 0x000000e0,
IMG_FMT_ASTC_2D_LDR_SRGB_6X6             = 0x000000e1,
IMG_FMT_ASTC_2D_LDR_SRGB_8X5             = 0x000000e2,
IMG_FMT_ASTC_2D_LDR_SRGB_8X6             = 0x000000e3,
IMG_FMT_ASTC_2D_LDR_SRGB_8X8             = 0x000000e4,
IMG_FMT_ASTC_2D_LDR_SRGB_10X5            = 0x000000e5,
IMG_FMT_ASTC_2D_LDR_SRGB_10X6            = 0x000000e6,
IMG_FMT_ASTC_2D_LDR_SRGB_10X8            = 0x000000e7,
IMG_FMT_ASTC_2D_LDR_SRGB_10X10           = 0x000000e8,
IMG_FMT_ASTC_2D_LDR_SRGB_12X10           = 0x000000e9,
IMG_FMT_ASTC_2D_LDR_SRGB_12X12           = 0x000000ea,
IMG_FMT_ASTC_3D_LDR_3X3X3                = 0x000000eb,
IMG_FMT_ASTC_3D_LDR_4X3X3                = 0x000000ec,
IMG_FMT_ASTC_3D_LDR_4X4X3                = 0x000000ed,
IMG_FMT_ASTC_3D_LDR_4X4X4                = 0x000000ee,
IMG_FMT_ASTC_3D_LDR_5X4X4                = 0x000000ef,
IMG_FMT_ASTC_3D_LDR_5X5X4                = 0x000000f0,
IMG_FMT_ASTC_3D_LDR_5X5X5                = 0x000000f1,
IMG_FMT_ASTC_3D_LDR_6X5X5                = 0x000000f2,
IMG_FMT_ASTC_3D_LDR_6X6X5                = 0x000000f3,
IMG_FMT_ASTC_3D_LDR_6X6X6                = 0x000000f4,
IMG_FMT_ASTC_3D_HDR_3X3X3                = 0x000000f5,
IMG_FMT_ASTC_3D_HDR_4X3X3                = 0x000000f6,
IMG_FMT_ASTC_3D_HDR_4X4X3                = 0x000000f7,
IMG_FMT_ASTC_3D_HDR_4X4X4                = 0x000000f8,
IMG_FMT_ASTC_3D_HDR_5X4X4                = 0x000000f9,
IMG_FMT_ASTC_3D_HDR_5X5X4                = 0x000000fa,
IMG_FMT_ASTC_3D_HDR_5X5X5                = 0x000000fb,
IMG_FMT_ASTC_3D_HDR_6X5X5                = 0x000000fc,
IMG_FMT_ASTC_3D_HDR_6X6X5                = 0x000000fd,
IMG_FMT_ASTC_3D_HDR_6X6X6                = 0x000000fe,
IMG_FMT_ASTC_3D_LDR_SRGB_3X3X3           = 0x000000ff,
IMG_FMT_ASTC_3D_LDR_SRGB_4X3X3           = 0x00000100,
IMG_FMT_ASTC_3D_LDR_SRGB_4X4X3           = 0x00000101,
IMG_FMT_ASTC_3D_LDR_SRGB_4X4X4           = 0x00000102,
IMG_FMT_ASTC_3D_LDR_SRGB_5X4X4           = 0x00000103,
IMG_FMT_ASTC_3D_LDR_SRGB_5X5X4           = 0x00000104,
IMG_FMT_ASTC_3D_LDR_SRGB_5X5X5           = 0x00000105,
IMG_FMT_ASTC_3D_LDR_SRGB_6X5X5           = 0x00000106,
IMG_FMT_ASTC_3D_LDR_SRGB_6X6X5           = 0x00000107,
IMG_FMT_ASTC_3D_LDR_SRGB_6X6X6           = 0x00000108,
IMG_FMT_MM_8_UNORM                       = 0x00000109,
IMG_FMT_MM_8_UINT                        = 0x0000010a,
IMG_FMT_MM_8_8_UNORM                     = 0x0000010b,
IMG_FMT_MM_8_8_UINT                      = 0x0000010c,
IMG_FMT_MM_8_8_8_8_UNORM                 = 0x0000010d,
IMG_FMT_MM_8_8_8_8_UINT                  = 0x0000010e,
IMG_FMT_MM_VYUY8_UNORM                   = 0x0000010f,
IMG_FMT_MM_VYUY8_UINT                    = 0x00000110,
IMG_FMT_MM_10_11_11_UNORM                = 0x00000111,
IMG_FMT_MM_10_11_11_UINT                 = 0x00000112,
IMG_FMT_MM_2_10_10_10_UNORM              = 0x00000113,
IMG_FMT_MM_2_10_10_10_UINT               = 0x00000114,
IMG_FMT_MM_16_16_16_16_UNORM             = 0x00000115,
IMG_FMT_MM_16_16_16_16_UINT              = 0x00000116,
IMG_FMT_MM_10_IN_16_UNORM                = 0x00000117,
IMG_FMT_MM_10_IN_16_UINT                 = 0x00000118,
IMG_FMT_MM_10_IN_16_16_UNORM             = 0x00000119,
IMG_FMT_MM_10_IN_16_16_UINT              = 0x0000011a,
IMG_FMT_MM_10_IN_16_16_16_16_UNORM       = 0x0000011b,
IMG_FMT_MM_10_IN_16_16_16_16_UINT        = 0x0000011c,
IMG_FMT_RESERVED_285                     = 0x0000011d,
IMG_FMT_RESERVED_286                     = 0x0000011e,
IMG_FMT_RESERVED_287                     = 0x0000011f,
IMG_FMT_RESERVED_288                     = 0x00000120,
IMG_FMT_RESERVED_289                     = 0x00000121,
IMG_FMT_RESERVED_290                     = 0x00000122,
IMG_FMT_RESERVED_291                     = 0x00000123,
IMG_FMT_RESERVED_292                     = 0x00000124,
IMG_FMT_RESERVED_293                     = 0x00000125,
IMG_FMT_RESERVED_294                     = 0x00000126,
IMG_FMT_RESERVED_295                     = 0x00000127,
IMG_FMT_RESERVED_296                     = 0x00000128,
IMG_FMT_RESERVED_297                     = 0x00000129,
IMG_FMT_RESERVED_298                     = 0x0000012a,
IMG_FMT_RESERVED_299                     = 0x0000012b,
IMG_FMT_RESERVED_300                     = 0x0000012c,
IMG_FMT_RESERVED_301                     = 0x0000012d,
IMG_FMT_RESERVED_302                     = 0x0000012e,
IMG_FMT_RESERVED_303                     = 0x0000012f,
IMG_FMT_RESERVED_304                     = 0x00000130,
IMG_FMT_RESERVED_305                     = 0x00000131,
IMG_FMT_RESERVED_306                     = 0x00000132,
IMG_FMT_RESERVED_307                     = 0x00000133,
IMG_FMT_RESERVED_308                     = 0x00000134,
IMG_FMT_RESERVED_309                     = 0x00000135,
IMG_FMT_RESERVED_310                     = 0x00000136,
IMG_FMT_RESERVED_311                     = 0x00000137,
IMG_FMT_RESERVED_312                     = 0x00000138,
IMG_FMT_RESERVED_313                     = 0x00000139,
IMG_FMT_RESERVED_314                     = 0x0000013a,
IMG_FMT_RESERVED_315                     = 0x0000013b,
IMG_FMT_RESERVED_316                     = 0x0000013c,
IMG_FMT_RESERVED_317                     = 0x0000013d,
IMG_FMT_RESERVED_318                     = 0x0000013e,
IMG_FMT_RESERVED_319                     = 0x0000013f,
IMG_FMT_RESERVED_320                     = 0x00000140,
IMG_FMT_RESERVED_321                     = 0x00000141,
IMG_FMT_RESERVED_322                     = 0x00000142,
IMG_FMT_RESERVED_323                     = 0x00000143,
IMG_FMT_RESERVED_324                     = 0x00000144,
IMG_FMT_RESERVED_325                     = 0x00000145,
IMG_FMT_RESERVED_326                     = 0x00000146,
IMG_FMT_RESERVED_327                     = 0x00000147,
IMG_FMT_RESERVED_328                     = 0x00000148,
IMG_FMT_RESERVED_329                     = 0x00000149,
IMG_FMT_RESERVED_330                     = 0x0000014a,
IMG_FMT_RESERVED_331                     = 0x0000014b,
IMG_FMT_RESERVED_332                     = 0x0000014c,
IMG_FMT_RESERVED_333                     = 0x0000014d,
IMG_FMT_RESERVED_334                     = 0x0000014e,
IMG_FMT_RESERVED_335                     = 0x0000014f,
IMG_FMT_RESERVED_336                     = 0x00000150,
IMG_FMT_RESERVED_337                     = 0x00000151,
IMG_FMT_RESERVED_338                     = 0x00000152,
IMG_FMT_RESERVED_339                     = 0x00000153,
IMG_FMT_RESERVED_340                     = 0x00000154,
IMG_FMT_RESERVED_341                     = 0x00000155,
IMG_FMT_RESERVED_342                     = 0x00000156,
IMG_FMT_RESERVED_343                     = 0x00000157,
IMG_FMT_RESERVED_344                     = 0x00000158,
IMG_FMT_RESERVED_345                     = 0x00000159,
IMG_FMT_RESERVED_346                     = 0x0000015a,
IMG_FMT_RESERVED_347                     = 0x0000015b,
IMG_FMT_RESERVED_348                     = 0x0000015c,
IMG_FMT_RESERVED_349                     = 0x0000015d,
IMG_FMT_RESERVED_350                     = 0x0000015e,
IMG_FMT_RESERVED_351                     = 0x0000015f,
IMG_FMT_RESERVED_352                     = 0x00000160,
IMG_FMT_RESERVED_353                     = 0x00000161,
IMG_FMT_RESERVED_354                     = 0x00000162,
IMG_FMT_RESERVED_355                     = 0x00000163,
IMG_FMT_RESERVED_356                     = 0x00000164,
IMG_FMT_RESERVED_357                     = 0x00000165,
IMG_FMT_RESERVED_358                     = 0x00000166,
IMG_FMT_RESERVED_359                     = 0x00000167,
IMG_FMT_RESERVED_360                     = 0x00000168,
IMG_FMT_RESERVED_361                     = 0x00000169,
IMG_FMT_RESERVED_362                     = 0x0000016a,
IMG_FMT_RESERVED_363                     = 0x0000016b,
IMG_FMT_RESERVED_364                     = 0x0000016c,
IMG_FMT_RESERVED_365                     = 0x0000016d,
IMG_FMT_RESERVED_366                     = 0x0000016e,
IMG_FMT_RESERVED_367                     = 0x0000016f,
IMG_FMT_RESERVED_368                     = 0x00000170,
IMG_FMT_RESERVED_369                     = 0x00000171,
IMG_FMT_RESERVED_370                     = 0x00000172,
IMG_FMT_RESERVED_371                     = 0x00000173,
IMG_FMT_RESERVED_372                     = 0x00000174,
IMG_FMT_RESERVED_373                     = 0x00000175,
IMG_FMT_RESERVED_374                     = 0x00000176,
IMG_FMT_RESERVED_375                     = 0x00000177,
IMG_FMT_RESERVED_376                     = 0x00000178,
IMG_FMT_RESERVED_377                     = 0x00000179,
IMG_FMT_RESERVED_378                     = 0x0000017a,
IMG_FMT_RESERVED_379                     = 0x0000017b,
IMG_FMT_RESERVED_380                     = 0x0000017c,
IMG_FMT_RESERVED_381                     = 0x0000017d,
IMG_FMT_RESERVED_382                     = 0x0000017e,
IMG_FMT_RESERVED_383                     = 0x0000017f,
IMG_FMT_RESERVED_384                     = 0x00000180,
IMG_FMT_RESERVED_385                     = 0x00000181,
IMG_FMT_RESERVED_386                     = 0x00000182,
IMG_FMT_RESERVED_387                     = 0x00000183,
IMG_FMT_RESERVED_388                     = 0x00000184,
IMG_FMT_RESERVED_389                     = 0x00000185,
IMG_FMT_RESERVED_390                     = 0x00000186,
IMG_FMT_RESERVED_391                     = 0x00000187,
IMG_FMT_RESERVED_392                     = 0x00000188,
IMG_FMT_RESERVED_393                     = 0x00000189,
IMG_FMT_RESERVED_394                     = 0x0000018a,
IMG_FMT_RESERVED_395                     = 0x0000018b,
IMG_FMT_RESERVED_396                     = 0x0000018c,
IMG_FMT_RESERVED_397                     = 0x0000018d,
IMG_FMT_RESERVED_398                     = 0x0000018e,
IMG_FMT_RESERVED_399                     = 0x0000018f,
IMG_FMT_RESERVED_400                     = 0x00000190,
IMG_FMT_RESERVED_401                     = 0x00000191,
IMG_FMT_RESERVED_402                     = 0x00000192,
IMG_FMT_RESERVED_403                     = 0x00000193,
IMG_FMT_RESERVED_404                     = 0x00000194,
IMG_FMT_RESERVED_405                     = 0x00000195,
IMG_FMT_RESERVED_406                     = 0x00000196,
IMG_FMT_RESERVED_407                     = 0x00000197,
IMG_FMT_RESERVED_408                     = 0x00000198,
IMG_FMT_RESERVED_409                     = 0x00000199,
IMG_FMT_RESERVED_410                     = 0x0000019a,
IMG_FMT_RESERVED_411                     = 0x0000019b,
IMG_FMT_RESERVED_412                     = 0x0000019c,
IMG_FMT_RESERVED_413                     = 0x0000019d,
IMG_FMT_RESERVED_414                     = 0x0000019e,
IMG_FMT_RESERVED_415                     = 0x0000019f,
IMG_FMT_RESERVED_416                     = 0x000001a0,
IMG_FMT_RESERVED_417                     = 0x000001a1,
IMG_FMT_RESERVED_418                     = 0x000001a2,
IMG_FMT_RESERVED_419                     = 0x000001a3,
IMG_FMT_RESERVED_420                     = 0x000001a4,
IMG_FMT_RESERVED_421                     = 0x000001a5,
IMG_FMT_RESERVED_422                     = 0x000001a6,
IMG_FMT_RESERVED_423                     = 0x000001a7,
IMG_FMT_RESERVED_424                     = 0x000001a8,
IMG_FMT_RESERVED_425                     = 0x000001a9,
IMG_FMT_RESERVED_426                     = 0x000001aa,
IMG_FMT_RESERVED_427                     = 0x000001ab,
IMG_FMT_RESERVED_428                     = 0x000001ac,
IMG_FMT_RESERVED_429                     = 0x000001ad,
IMG_FMT_RESERVED_430                     = 0x000001ae,
IMG_FMT_RESERVED_431                     = 0x000001af,
IMG_FMT_RESERVED_432                     = 0x000001b0,
IMG_FMT_RESERVED_433                     = 0x000001b1,
IMG_FMT_RESERVED_434                     = 0x000001b2,
IMG_FMT_RESERVED_435                     = 0x000001b3,
IMG_FMT_RESERVED_436                     = 0x000001b4,
IMG_FMT_RESERVED_437                     = 0x000001b5,
IMG_FMT_RESERVED_438                     = 0x000001b6,
IMG_FMT_RESERVED_439                     = 0x000001b7,
IMG_FMT_RESERVED_440                     = 0x000001b8,
IMG_FMT_RESERVED_441                     = 0x000001b9,
IMG_FMT_RESERVED_442                     = 0x000001ba,
IMG_FMT_RESERVED_443                     = 0x000001bb,
IMG_FMT_RESERVED_444                     = 0x000001bc,
IMG_FMT_RESERVED_445                     = 0x000001bd,
IMG_FMT_RESERVED_446                     = 0x000001be,
IMG_FMT_RESERVED_447                     = 0x000001bf,
IMG_FMT_RESERVED_448                     = 0x000001c0,
IMG_FMT_RESERVED_449                     = 0x000001c1,
IMG_FMT_RESERVED_450                     = 0x000001c2,
IMG_FMT_RESERVED_451                     = 0x000001c3,
IMG_FMT_RESERVED_452                     = 0x000001c4,
IMG_FMT_RESERVED_453                     = 0x000001c5,
IMG_FMT_RESERVED_454                     = 0x000001c6,
IMG_FMT_RESERVED_455                     = 0x000001c7,
IMG_FMT_RESERVED_456                     = 0x000001c8,
IMG_FMT_RESERVED_457                     = 0x000001c9,
IMG_FMT_RESERVED_458                     = 0x000001ca,
IMG_FMT_RESERVED_459                     = 0x000001cb,
IMG_FMT_RESERVED_460                     = 0x000001cc,
IMG_FMT_RESERVED_461                     = 0x000001cd,
IMG_FMT_RESERVED_462                     = 0x000001ce,
IMG_FMT_RESERVED_463                     = 0x000001cf,
IMG_FMT_RESERVED_464                     = 0x000001d0,
IMG_FMT_RESERVED_465                     = 0x000001d1,
IMG_FMT_RESERVED_466                     = 0x000001d2,
IMG_FMT_RESERVED_467                     = 0x000001d3,
IMG_FMT_RESERVED_468                     = 0x000001d4,
IMG_FMT_RESERVED_469                     = 0x000001d5,
IMG_FMT_RESERVED_470                     = 0x000001d6,
IMG_FMT_RESERVED_471                     = 0x000001d7,
IMG_FMT_RESERVED_472                     = 0x000001d8,
IMG_FMT_RESERVED_473                     = 0x000001d9,
IMG_FMT_RESERVED_474                     = 0x000001da,
IMG_FMT_RESERVED_475                     = 0x000001db,
IMG_FMT_RESERVED_476                     = 0x000001dc,
IMG_FMT_RESERVED_477                     = 0x000001dd,
IMG_FMT_RESERVED_478                     = 0x000001de,
IMG_FMT_RESERVED_479                     = 0x000001df,
IMG_FMT_RESERVED_480                     = 0x000001e0,
IMG_FMT_RESERVED_481                     = 0x000001e1,
IMG_FMT_RESERVED_482                     = 0x000001e2,
IMG_FMT_RESERVED_483                     = 0x000001e3,
IMG_FMT_RESERVED_484                     = 0x000001e4,
IMG_FMT_RESERVED_485                     = 0x000001e5,
IMG_FMT_RESERVED_486                     = 0x000001e6,
IMG_FMT_RESERVED_487                     = 0x000001e7,
IMG_FMT_RESERVED_488                     = 0x000001e8,
IMG_FMT_RESERVED_489                     = 0x000001e9,
IMG_FMT_RESERVED_490                     = 0x000001ea,
IMG_FMT_RESERVED_491                     = 0x000001eb,
IMG_FMT_RESERVED_492                     = 0x000001ec,
IMG_FMT_RESERVED_493                     = 0x000001ed,
IMG_FMT_RESERVED_494                     = 0x000001ee,
IMG_FMT_RESERVED_495                     = 0x000001ef,
IMG_FMT_RESERVED_496                     = 0x000001f0,
IMG_FMT_RESERVED_497                     = 0x000001f1,
IMG_FMT_RESERVED_498                     = 0x000001f2,
IMG_FMT_RESERVED_499                     = 0x000001f3,
IMG_FMT_RESERVED_500                     = 0x000001f4,
IMG_FMT_RESERVED_501                     = 0x000001f5,
IMG_FMT_RESERVED_502                     = 0x000001f6,
IMG_FMT_RESERVED_503                     = 0x000001f7,
IMG_FMT_RESERVED_504                     = 0x000001f8,
IMG_FMT_RESERVED_505                     = 0x000001f9,
IMG_FMT_RESERVED_506                     = 0x000001fa,
IMG_FMT_RESERVED_507                     = 0x000001fb,
IMG_FMT_RESERVED_508                     = 0x000001fc,
IMG_FMT_RESERVED_509                     = 0x000001fd,
IMG_FMT_RESERVED_510                     = 0x000001fe,
IMG_FMT_RESERVED_511                     = 0x000001ff,
} IMG_FMT;

typedef enum NUM_BANKS_BC_ENUM {
ADDR_NUM_BANKS_BC_BANKS_1                = 0x00000000,
ADDR_NUM_BANKS_BC_BANKS_2                = 0x00000001,
ADDR_NUM_BANKS_BC_BANKS_4                = 0x00000002,
ADDR_NUM_BANKS_BC_BANKS_8                = 0x00000003,
ADDR_NUM_BANKS_BC_BANKS_16               = 0x00000004,
} NUM_BANKS_BC_ENUM;

typedef enum NUM_PIPES_BC_ENUM {
ADDR_NUM_PIPES_BC_P8                     = 0x00000000,
ADDR_NUM_PIPES_BC_P16                    = 0x00000001,
} NUM_PIPES_BC_ENUM;

typedef enum PH_PERFCNT_SEL {
PH_SC0_SRPS_WINDOW_VALID                 = 0x00000000,
PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000001,
PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES          = 0x00000002,
PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x00000003,
PH_SC0_ARB_STALLED_FROM_BELOW            = 0x00000004,
PH_SC0_ARB_STARVED_FROM_ABOVE            = 0x00000005,
PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006,
PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007,
PH_SC0_ARB_BUSY                          = 0x00000008,
PH_SC0_ARB_PA_BUSY_SOP                   = 0x00000009,
PH_SC0_ARB_EOP_POP_SYNC_POP              = 0x0000000a,
PH_SC0_ARB_EVENT_SYNC_POP                = 0x0000000b,
PH_SC0_PS_ENG_MULTICYCLE_BUBBLE          = 0x0000000c,
PH_SC0_EOP_SYNC_WINDOW                   = 0x0000000d,
PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x0000000e,
PH_SC0_BUSY_CNT_NOT_ZERO                 = 0x0000000f,
PH_SC0_SEND                              = 0x00000010,
PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000011,
PH_SC0_CREDIT_AT_MAX                     = 0x00000012,
PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x00000013,
PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000014,
PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000015,
PH_SC0_GFX_PIPE0_TO_1_TRANSITION         = 0x00000016,
PH_SC0_GFX_PIPE1_TO_0_TRANSITION         = 0x00000017,
PH_SC0_PA0_DATA_FIFO_RD                  = 0x00000018,
PH_SC0_PA0_DATA_FIFO_WE                  = 0x00000019,
PH_SC0_PA0_FIFO_EMPTY                    = 0x0000001a,
PH_SC0_PA0_FIFO_FULL                     = 0x0000001b,
PH_SC0_PA0_NULL_WE                       = 0x0000001c,
PH_SC0_PA0_EVENT_WE                      = 0x0000001d,
PH_SC0_PA0_FPOV_WE                       = 0x0000001e,
PH_SC0_PA0_LPOV_WE                       = 0x0000001f,
PH_SC0_PA0_EOP_WE                        = 0x00000020,
PH_SC0_PA0_DATA_FIFO_EOP_RD              = 0x00000021,
PH_SC0_PA0_EOPG_WE                       = 0x00000022,
PH_SC0_PA0_DEALLOC_4_0_RD                = 0x00000023,
PH_SC0_PA1_DATA_FIFO_RD                  = 0x00000024,
PH_SC0_PA1_DATA_FIFO_WE                  = 0x00000025,
PH_SC0_PA1_FIFO_EMPTY                    = 0x00000026,
PH_SC0_PA1_FIFO_FULL                     = 0x00000027,
PH_SC0_PA1_NULL_WE                       = 0x00000028,
PH_SC0_PA1_EVENT_WE                      = 0x00000029,
PH_SC0_PA1_FPOV_WE                       = 0x0000002a,
PH_SC0_PA1_LPOV_WE                       = 0x0000002b,
PH_SC0_PA1_EOP_WE                        = 0x0000002c,
PH_SC0_PA1_DATA_FIFO_EOP_RD              = 0x0000002d,
PH_SC0_PA1_EOPG_WE                       = 0x0000002e,
PH_SC0_PA1_DEALLOC_4_0_RD                = 0x0000002f,
PH_SC0_PA2_DATA_FIFO_RD                  = 0x00000030,
PH_SC0_PA2_DATA_FIFO_WE                  = 0x00000031,
PH_SC0_PA2_FIFO_EMPTY                    = 0x00000032,
PH_SC0_PA2_FIFO_FULL                     = 0x00000033,
PH_SC0_PA2_NULL_WE                       = 0x00000034,
PH_SC0_PA2_EVENT_WE                      = 0x00000035,
PH_SC0_PA2_FPOV_WE                       = 0x00000036,
PH_SC0_PA2_LPOV_WE                       = 0x00000037,
PH_SC0_PA2_EOP_WE                        = 0x00000038,
PH_SC0_PA2_DATA_FIFO_EOP_RD              = 0x00000039,
PH_SC0_PA2_EOPG_WE                       = 0x0000003a,
PH_SC0_PA2_DEALLOC_4_0_RD                = 0x0000003b,
PH_SC0_PA3_DATA_FIFO_RD                  = 0x0000003c,
PH_SC0_PA3_DATA_FIFO_WE                  = 0x0000003d,
PH_SC0_PA3_FIFO_EMPTY                    = 0x0000003e,
PH_SC0_PA3_FIFO_FULL                     = 0x0000003f,
PH_SC0_PA3_NULL_WE                       = 0x00000040,
PH_SC0_PA3_EVENT_WE                      = 0x00000041,
PH_SC0_PA3_FPOV_WE                       = 0x00000042,
PH_SC0_PA3_LPOV_WE                       = 0x00000043,
PH_SC0_PA3_EOP_WE                        = 0x00000044,
PH_SC0_PA3_DATA_FIFO_EOP_RD              = 0x00000045,
PH_SC0_PA3_EOPG_WE                       = 0x00000046,
PH_SC0_PA3_DEALLOC_4_0_RD                = 0x00000047,
PH_SC0_PA4_DATA_FIFO_RD                  = 0x00000048,
PH_SC0_PA4_DATA_FIFO_WE                  = 0x00000049,
PH_SC0_PA4_FIFO_EMPTY                    = 0x0000004a,
PH_SC0_PA4_FIFO_FULL                     = 0x0000004b,
PH_SC0_PA4_NULL_WE                       = 0x0000004c,
PH_SC0_PA4_EVENT_WE                      = 0x0000004d,
PH_SC0_PA4_FPOV_WE                       = 0x0000004e,
PH_SC0_PA4_LPOV_WE                       = 0x0000004f,
PH_SC0_PA4_EOP_WE                        = 0x00000050,
PH_SC0_PA4_DATA_FIFO_EOP_RD              = 0x00000051,
PH_SC0_PA4_EOPG_WE                       = 0x00000052,
PH_SC0_PA4_DEALLOC_4_0_RD                = 0x00000053,
PH_SC0_PA5_DATA_FIFO_RD                  = 0x00000054,
PH_SC0_PA5_DATA_FIFO_WE                  = 0x00000055,
PH_SC0_PA5_FIFO_EMPTY                    = 0x00000056,
PH_SC0_PA5_FIFO_FULL                     = 0x00000057,
PH_SC0_PA5_NULL_WE                       = 0x00000058,
PH_SC0_PA5_EVENT_WE                      = 0x00000059,
PH_SC0_PA5_FPOV_WE                       = 0x0000005a,
PH_SC0_PA5_LPOV_WE                       = 0x0000005b,
PH_SC0_PA5_EOP_WE                        = 0x0000005c,
PH_SC0_PA5_DATA_FIFO_EOP_RD              = 0x0000005d,
PH_SC0_PA5_EOPG_WE                       = 0x0000005e,
PH_SC0_PA5_DEALLOC_4_0_RD                = 0x0000005f,
PH_SC0_PA6_DATA_FIFO_RD                  = 0x00000060,
PH_SC0_PA6_DATA_FIFO_WE                  = 0x00000061,
PH_SC0_PA6_FIFO_EMPTY                    = 0x00000062,
PH_SC0_PA6_FIFO_FULL                     = 0x00000063,
PH_SC0_PA6_NULL_WE                       = 0x00000064,
PH_SC0_PA6_EVENT_WE                      = 0x00000065,
PH_SC0_PA6_FPOV_WE                       = 0x00000066,
PH_SC0_PA6_LPOV_WE                       = 0x00000067,
PH_SC0_PA6_EOP_WE                        = 0x00000068,
PH_SC0_PA6_DATA_FIFO_EOP_RD              = 0x00000069,
PH_SC0_PA6_EOPG_WE                       = 0x0000006a,
PH_SC0_PA6_DEALLOC_4_0_RD                = 0x0000006b,
PH_SC0_PA7_DATA_FIFO_RD                  = 0x0000006c,
PH_SC0_PA7_DATA_FIFO_WE                  = 0x0000006d,
PH_SC0_PA7_FIFO_EMPTY                    = 0x0000006e,
PH_SC0_PA7_FIFO_FULL                     = 0x0000006f,
PH_SC0_PA7_NULL_WE                       = 0x00000070,
PH_SC0_PA7_EVENT_WE                      = 0x00000071,
PH_SC0_PA7_FPOV_WE                       = 0x00000072,
PH_SC0_PA7_LPOV_WE                       = 0x00000073,
PH_SC0_PA7_EOP_WE                        = 0x00000074,
PH_SC0_PA7_DATA_FIFO_EOP_RD              = 0x00000075,
PH_SC0_PA7_EOPG_WE                       = 0x00000076,
PH_SC0_PA7_DEALLOC_4_0_RD                = 0x00000077,
PH_SC1_SRPS_WINDOW_VALID                 = 0x00000078,
PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000079,
PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000007a,
PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000007b,
PH_SC1_ARB_STALLED_FROM_BELOW            = 0x0000007c,
PH_SC1_ARB_STARVED_FROM_ABOVE            = 0x0000007d,
PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e,
PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f,
PH_SC1_ARB_BUSY                          = 0x00000080,
PH_SC1_ARB_PA_BUSY_SOP                   = 0x00000081,
PH_SC1_ARB_EOP_POP_SYNC_POP              = 0x00000082,
PH_SC1_ARB_EVENT_SYNC_POP                = 0x00000083,
PH_SC1_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000084,
PH_SC1_EOP_SYNC_WINDOW                   = 0x00000085,
PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000086,
PH_SC1_BUSY_CNT_NOT_ZERO                 = 0x00000087,
PH_SC1_SEND                              = 0x00000088,
PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000089,
PH_SC1_CREDIT_AT_MAX                     = 0x0000008a,
PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000008b,
PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008c,
PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008d,
PH_SC1_GFX_PIPE0_TO_1_TRANSITION         = 0x0000008e,
PH_SC1_GFX_PIPE1_TO_0_TRANSITION         = 0x0000008f,
PH_SC1_PA0_DATA_FIFO_RD                  = 0x00000090,
PH_SC1_PA0_DATA_FIFO_WE                  = 0x00000091,
PH_SC1_PA0_FIFO_EMPTY                    = 0x00000092,
PH_SC1_PA0_FIFO_FULL                     = 0x00000093,
PH_SC1_PA0_NULL_WE                       = 0x00000094,
PH_SC1_PA0_EVENT_WE                      = 0x00000095,
PH_SC1_PA0_FPOV_WE                       = 0x00000096,
PH_SC1_PA0_LPOV_WE                       = 0x00000097,
PH_SC1_PA0_EOP_WE                        = 0x00000098,
PH_SC1_PA0_DATA_FIFO_EOP_RD              = 0x00000099,
PH_SC1_PA0_EOPG_WE                       = 0x0000009a,
PH_SC1_PA0_DEALLOC_4_0_RD                = 0x0000009b,
PH_SC1_PA1_DATA_FIFO_RD                  = 0x0000009c,
PH_SC1_PA1_DATA_FIFO_WE                  = 0x0000009d,
PH_SC1_PA1_FIFO_EMPTY                    = 0x0000009e,
PH_SC1_PA1_FIFO_FULL                     = 0x0000009f,
PH_SC1_PA1_NULL_WE                       = 0x000000a0,
PH_SC1_PA1_EVENT_WE                      = 0x000000a1,
PH_SC1_PA1_FPOV_WE                       = 0x000000a2,
PH_SC1_PA1_LPOV_WE                       = 0x000000a3,
PH_SC1_PA1_EOP_WE                        = 0x000000a4,
PH_SC1_PA1_DATA_FIFO_EOP_RD              = 0x000000a5,
PH_SC1_PA1_EOPG_WE                       = 0x000000a6,
PH_SC1_PA1_DEALLOC_4_0_RD                = 0x000000a7,
PH_SC1_PA2_DATA_FIFO_RD                  = 0x000000a8,
PH_SC1_PA2_DATA_FIFO_WE                  = 0x000000a9,
PH_SC1_PA2_FIFO_EMPTY                    = 0x000000aa,
PH_SC1_PA2_FIFO_FULL                     = 0x000000ab,
PH_SC1_PA2_NULL_WE                       = 0x000000ac,
PH_SC1_PA2_EVENT_WE                      = 0x000000ad,
PH_SC1_PA2_FPOV_WE                       = 0x000000ae,
PH_SC1_PA2_LPOV_WE                       = 0x000000af,
PH_SC1_PA2_EOP_WE                        = 0x000000b0,
PH_SC1_PA2_DATA_FIFO_EOP_RD              = 0x000000b1,
PH_SC1_PA2_EOPG_WE                       = 0x000000b2,
PH_SC1_PA2_DEALLOC_4_0_RD                = 0x000000b3,
PH_SC1_PA3_DATA_FIFO_RD                  = 0x000000b4,
PH_SC1_PA3_DATA_FIFO_WE                  = 0x000000b5,
PH_SC1_PA3_FIFO_EMPTY                    = 0x000000b6,
PH_SC1_PA3_FIFO_FULL                     = 0x000000b7,
PH_SC1_PA3_NULL_WE                       = 0x000000b8,
PH_SC1_PA3_EVENT_WE                      = 0x000000b9,
PH_SC1_PA3_FPOV_WE                       = 0x000000ba,
PH_SC1_PA3_LPOV_WE                       = 0x000000bb,
PH_SC1_PA3_EOP_WE                        = 0x000000bc,
PH_SC1_PA3_DATA_FIFO_EOP_RD              = 0x000000bd,
PH_SC1_PA3_EOPG_WE                       = 0x000000be,
PH_SC1_PA3_DEALLOC_4_0_RD                = 0x000000bf,
PH_SC1_PA4_DATA_FIFO_RD                  = 0x000000c0,
PH_SC1_PA4_DATA_FIFO_WE                  = 0x000000c1,
PH_SC1_PA4_FIFO_EMPTY                    = 0x000000c2,
PH_SC1_PA4_FIFO_FULL                     = 0x000000c3,
PH_SC1_PA4_NULL_WE                       = 0x000000c4,
PH_SC1_PA4_EVENT_WE                      = 0x000000c5,
PH_SC1_PA4_FPOV_WE                       = 0x000000c6,
PH_SC1_PA4_LPOV_WE                       = 0x000000c7,
PH_SC1_PA4_EOP_WE                        = 0x000000c8,
PH_SC1_PA4_DATA_FIFO_EOP_RD              = 0x000000c9,
PH_SC1_PA4_EOPG_WE                       = 0x000000ca,
PH_SC1_PA4_DEALLOC_4_0_RD                = 0x000000cb,
PH_SC1_PA5_DATA_FIFO_RD                  = 0x000000cc,
PH_SC1_PA5_DATA_FIFO_WE                  = 0x000000cd,
PH_SC1_PA5_FIFO_EMPTY                    = 0x000000ce,
PH_SC1_PA5_FIFO_FULL                     = 0x000000cf,
PH_SC1_PA5_NULL_WE                       = 0x000000d0,
PH_SC1_PA5_EVENT_WE                      = 0x000000d1,
PH_SC1_PA5_FPOV_WE                       = 0x000000d2,
PH_SC1_PA5_LPOV_WE                       = 0x000000d3,
PH_SC1_PA5_EOP_WE                        = 0x000000d4,
PH_SC1_PA5_DATA_FIFO_EOP_RD              = 0x000000d5,
PH_SC1_PA5_EOPG_WE                       = 0x000000d6,
PH_SC1_PA5_DEALLOC_4_0_RD                = 0x000000d7,
PH_SC1_PA6_DATA_FIFO_RD                  = 0x000000d8,
PH_SC1_PA6_DATA_FIFO_WE                  = 0x000000d9,
PH_SC1_PA6_FIFO_EMPTY                    = 0x000000da,
PH_SC1_PA6_FIFO_FULL                     = 0x000000db,
PH_SC1_PA6_NULL_WE                       = 0x000000dc,
PH_SC1_PA6_EVENT_WE                      = 0x000000dd,
PH_SC1_PA6_FPOV_WE                       = 0x000000de,
PH_SC1_PA6_LPOV_WE                       = 0x000000df,
PH_SC1_PA6_EOP_WE                        = 0x000000e0,
PH_SC1_PA6_DATA_FIFO_EOP_RD              = 0x000000e1,
PH_SC1_PA6_EOPG_WE                       = 0x000000e2,
PH_SC1_PA6_DEALLOC_4_0_RD                = 0x000000e3,
PH_SC1_PA7_DATA_FIFO_RD                  = 0x000000e4,
PH_SC1_PA7_DATA_FIFO_WE                  = 0x000000e5,
PH_SC1_PA7_FIFO_EMPTY                    = 0x000000e6,
PH_SC1_PA7_FIFO_FULL                     = 0x000000e7,
PH_SC1_PA7_NULL_WE                       = 0x000000e8,
PH_SC1_PA7_EVENT_WE                      = 0x000000e9,
PH_SC1_PA7_FPOV_WE                       = 0x000000ea,
PH_SC1_PA7_LPOV_WE                       = 0x000000eb,
PH_SC1_PA7_EOP_WE                        = 0x000000ec,
PH_SC1_PA7_DATA_FIFO_EOP_RD              = 0x000000ed,
PH_SC1_PA7_EOPG_WE                       = 0x000000ee,
PH_SC1_PA7_DEALLOC_4_0_RD                = 0x000000ef,
PH_SC2_SRPS_WINDOW_VALID                 = 0x000000f0,
PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000000f1,
PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000000f2,
PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000000f3,
PH_SC2_ARB_STALLED_FROM_BELOW            = 0x000000f4,
PH_SC2_ARB_STARVED_FROM_ABOVE            = 0x000000f5,
PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6,
PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7,
PH_SC2_ARB_BUSY                          = 0x000000f8,
PH_SC2_ARB_PA_BUSY_SOP                   = 0x000000f9,
PH_SC2_ARB_EOP_POP_SYNC_POP              = 0x000000fa,
PH_SC2_ARB_EVENT_SYNC_POP                = 0x000000fb,
PH_SC2_PS_ENG_MULTICYCLE_BUBBLE          = 0x000000fc,
PH_SC2_EOP_SYNC_WINDOW                   = 0x000000fd,
PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000000fe,
PH_SC2_BUSY_CNT_NOT_ZERO                 = 0x000000ff,
PH_SC2_SEND                              = 0x00000100,
PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000101,
PH_SC2_CREDIT_AT_MAX                     = 0x00000102,
PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x00000103,
PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000104,
PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000105,
PH_SC2_GFX_PIPE0_TO_1_TRANSITION         = 0x00000106,
PH_SC2_GFX_PIPE1_TO_0_TRANSITION         = 0x00000107,
PH_SC2_PA0_DATA_FIFO_RD                  = 0x00000108,
PH_SC2_PA0_DATA_FIFO_WE                  = 0x00000109,
PH_SC2_PA0_FIFO_EMPTY                    = 0x0000010a,
PH_SC2_PA0_FIFO_FULL                     = 0x0000010b,
PH_SC2_PA0_NULL_WE                       = 0x0000010c,
PH_SC2_PA0_EVENT_WE                      = 0x0000010d,
PH_SC2_PA0_FPOV_WE                       = 0x0000010e,
PH_SC2_PA0_LPOV_WE                       = 0x0000010f,
PH_SC2_PA0_EOP_WE                        = 0x00000110,
PH_SC2_PA0_DATA_FIFO_EOP_RD              = 0x00000111,
PH_SC2_PA0_EOPG_WE                       = 0x00000112,
PH_SC2_PA0_DEALLOC_4_0_RD                = 0x00000113,
PH_SC2_PA1_DATA_FIFO_RD                  = 0x00000114,
PH_SC2_PA1_DATA_FIFO_WE                  = 0x00000115,
PH_SC2_PA1_FIFO_EMPTY                    = 0x00000116,
PH_SC2_PA1_FIFO_FULL                     = 0x00000117,
PH_SC2_PA1_NULL_WE                       = 0x00000118,
PH_SC2_PA1_EVENT_WE                      = 0x00000119,
PH_SC2_PA1_FPOV_WE                       = 0x0000011a,
PH_SC2_PA1_LPOV_WE                       = 0x0000011b,
PH_SC2_PA1_EOP_WE                        = 0x0000011c,
PH_SC2_PA1_DATA_FIFO_EOP_RD              = 0x0000011d,
PH_SC2_PA1_EOPG_WE                       = 0x0000011e,
PH_SC2_PA1_DEALLOC_4_0_RD                = 0x0000011f,
PH_SC2_PA2_DATA_FIFO_RD                  = 0x00000120,
PH_SC2_PA2_DATA_FIFO_WE                  = 0x00000121,
PH_SC2_PA2_FIFO_EMPTY                    = 0x00000122,
PH_SC2_PA2_FIFO_FULL                     = 0x00000123,
PH_SC2_PA2_NULL_WE                       = 0x00000124,
PH_SC2_PA2_EVENT_WE                      = 0x00000125,
PH_SC2_PA2_FPOV_WE                       = 0x00000126,
PH_SC2_PA2_LPOV_WE                       = 0x00000127,
PH_SC2_PA2_EOP_WE                        = 0x00000128,
PH_SC2_PA2_DATA_FIFO_EOP_RD              = 0x00000129,
PH_SC2_PA2_EOPG_WE                       = 0x0000012a,
PH_SC2_PA2_DEALLOC_4_0_RD                = 0x0000012b,
PH_SC2_PA3_DATA_FIFO_RD                  = 0x0000012c,
PH_SC2_PA3_DATA_FIFO_WE                  = 0x0000012d,
PH_SC2_PA3_FIFO_EMPTY                    = 0x0000012e,
PH_SC2_PA3_FIFO_FULL                     = 0x0000012f,
PH_SC2_PA3_NULL_WE                       = 0x00000130,
PH_SC2_PA3_EVENT_WE                      = 0x00000131,
PH_SC2_PA3_FPOV_WE                       = 0x00000132,
PH_SC2_PA3_LPOV_WE                       = 0x00000133,
PH_SC2_PA3_EOP_WE                        = 0x00000134,
PH_SC2_PA3_DATA_FIFO_EOP_RD              = 0x00000135,
PH_SC2_PA3_EOPG_WE                       = 0x00000136,
PH_SC2_PA3_DEALLOC_4_0_RD                = 0x00000137,
PH_SC2_PA4_DATA_FIFO_RD                  = 0x00000138,
PH_SC2_PA4_DATA_FIFO_WE                  = 0x00000139,
PH_SC2_PA4_FIFO_EMPTY                    = 0x0000013a,
PH_SC2_PA4_FIFO_FULL                     = 0x0000013b,
PH_SC2_PA4_NULL_WE                       = 0x0000013c,
PH_SC2_PA4_EVENT_WE                      = 0x0000013d,
PH_SC2_PA4_FPOV_WE                       = 0x0000013e,
PH_SC2_PA4_LPOV_WE                       = 0x0000013f,
PH_SC2_PA4_EOP_WE                        = 0x00000140,
PH_SC2_PA4_DATA_FIFO_EOP_RD              = 0x00000141,
PH_SC2_PA4_EOPG_WE                       = 0x00000142,
PH_SC2_PA4_DEALLOC_4_0_RD                = 0x00000143,
PH_SC2_PA5_DATA_FIFO_RD                  = 0x00000144,
PH_SC2_PA5_DATA_FIFO_WE                  = 0x00000145,
PH_SC2_PA5_FIFO_EMPTY                    = 0x00000146,
PH_SC2_PA5_FIFO_FULL                     = 0x00000147,
PH_SC2_PA5_NULL_WE                       = 0x00000148,
PH_SC2_PA5_EVENT_WE                      = 0x00000149,
PH_SC2_PA5_FPOV_WE                       = 0x0000014a,
PH_SC2_PA5_LPOV_WE                       = 0x0000014b,
PH_SC2_PA5_EOP_WE                        = 0x0000014c,
PH_SC2_PA5_DATA_FIFO_EOP_RD              = 0x0000014d,
PH_SC2_PA5_EOPG_WE                       = 0x0000014e,
PH_SC2_PA5_DEALLOC_4_0_RD                = 0x0000014f,
PH_SC2_PA6_DATA_FIFO_RD                  = 0x00000150,
PH_SC2_PA6_DATA_FIFO_WE                  = 0x00000151,
PH_SC2_PA6_FIFO_EMPTY                    = 0x00000152,
PH_SC2_PA6_FIFO_FULL                     = 0x00000153,
PH_SC2_PA6_NULL_WE                       = 0x00000154,
PH_SC2_PA6_EVENT_WE                      = 0x00000155,
PH_SC2_PA6_FPOV_WE                       = 0x00000156,
PH_SC2_PA6_LPOV_WE                       = 0x00000157,
PH_SC2_PA6_EOP_WE                        = 0x00000158,
PH_SC2_PA6_DATA_FIFO_EOP_RD              = 0x00000159,
PH_SC2_PA6_EOPG_WE                       = 0x0000015a,
PH_SC2_PA6_DEALLOC_4_0_RD                = 0x0000015b,
PH_SC2_PA7_DATA_FIFO_RD                  = 0x0000015c,
PH_SC2_PA7_DATA_FIFO_WE                  = 0x0000015d,
PH_SC2_PA7_FIFO_EMPTY                    = 0x0000015e,
PH_SC2_PA7_FIFO_FULL                     = 0x0000015f,
PH_SC2_PA7_NULL_WE                       = 0x00000160,
PH_SC2_PA7_EVENT_WE                      = 0x00000161,
PH_SC2_PA7_FPOV_WE                       = 0x00000162,
PH_SC2_PA7_LPOV_WE                       = 0x00000163,
PH_SC2_PA7_EOP_WE                        = 0x00000164,
PH_SC2_PA7_DATA_FIFO_EOP_RD              = 0x00000165,
PH_SC2_PA7_EOPG_WE                       = 0x00000166,
PH_SC2_PA7_DEALLOC_4_0_RD                = 0x00000167,
PH_SC3_SRPS_WINDOW_VALID                 = 0x00000168,
PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000169,
PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000016a,
PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000016b,
PH_SC3_ARB_STALLED_FROM_BELOW            = 0x0000016c,
PH_SC3_ARB_STARVED_FROM_ABOVE            = 0x0000016d,
PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e,
PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f,
PH_SC3_ARB_BUSY                          = 0x00000170,
PH_SC3_ARB_PA_BUSY_SOP                   = 0x00000171,
PH_SC3_ARB_EOP_POP_SYNC_POP              = 0x00000172,
PH_SC3_ARB_EVENT_SYNC_POP                = 0x00000173,
PH_SC3_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000174,
PH_SC3_EOP_SYNC_WINDOW                   = 0x00000175,
PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000176,
PH_SC3_BUSY_CNT_NOT_ZERO                 = 0x00000177,
PH_SC3_SEND                              = 0x00000178,
PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000179,
PH_SC3_CREDIT_AT_MAX                     = 0x0000017a,
PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000017b,
PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017c,
PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017d,
PH_SC3_GFX_PIPE0_TO_1_TRANSITION         = 0x0000017e,
PH_SC3_GFX_PIPE1_TO_0_TRANSITION         = 0x0000017f,
PH_SC3_PA0_DATA_FIFO_RD                  = 0x00000180,
PH_SC3_PA0_DATA_FIFO_WE                  = 0x00000181,
PH_SC3_PA0_FIFO_EMPTY                    = 0x00000182,
PH_SC3_PA0_FIFO_FULL                     = 0x00000183,
PH_SC3_PA0_NULL_WE                       = 0x00000184,
PH_SC3_PA0_EVENT_WE                      = 0x00000185,
PH_SC3_PA0_FPOV_WE                       = 0x00000186,
PH_SC3_PA0_LPOV_WE                       = 0x00000187,
PH_SC3_PA0_EOP_WE                        = 0x00000188,
PH_SC3_PA0_DATA_FIFO_EOP_RD              = 0x00000189,
PH_SC3_PA0_EOPG_WE                       = 0x0000018a,
PH_SC3_PA0_DEALLOC_4_0_RD                = 0x0000018b,
PH_SC3_PA1_DATA_FIFO_RD                  = 0x0000018c,
PH_SC3_PA1_DATA_FIFO_WE                  = 0x0000018d,
PH_SC3_PA1_FIFO_EMPTY                    = 0x0000018e,
PH_SC3_PA1_FIFO_FULL                     = 0x0000018f,
PH_SC3_PA1_NULL_WE                       = 0x00000190,
PH_SC3_PA1_EVENT_WE                      = 0x00000191,
PH_SC3_PA1_FPOV_WE                       = 0x00000192,
PH_SC3_PA1_LPOV_WE                       = 0x00000193,
PH_SC3_PA1_EOP_WE                        = 0x00000194,
PH_SC3_PA1_DATA_FIFO_EOP_RD              = 0x00000195,
PH_SC3_PA1_EOPG_WE                       = 0x00000196,
PH_SC3_PA1_DEALLOC_4_0_RD                = 0x00000197,
PH_SC3_PA2_DATA_FIFO_RD                  = 0x00000198,
PH_SC3_PA2_DATA_FIFO_WE                  = 0x00000199,
PH_SC3_PA2_FIFO_EMPTY                    = 0x0000019a,
PH_SC3_PA2_FIFO_FULL                     = 0x0000019b,
PH_SC3_PA2_NULL_WE                       = 0x0000019c,
PH_SC3_PA2_EVENT_WE                      = 0x0000019d,
PH_SC3_PA2_FPOV_WE                       = 0x0000019e,
PH_SC3_PA2_LPOV_WE                       = 0x0000019f,
PH_SC3_PA2_EOP_WE                        = 0x000001a0,
PH_SC3_PA2_DATA_FIFO_EOP_RD              = 0x000001a1,
PH_SC3_PA2_EOPG_WE                       = 0x000001a2,
PH_SC3_PA2_DEALLOC_4_0_RD                = 0x000001a3,
PH_SC3_PA3_DATA_FIFO_RD                  = 0x000001a4,
PH_SC3_PA3_DATA_FIFO_WE                  = 0x000001a5,
PH_SC3_PA3_FIFO_EMPTY                    = 0x000001a6,
PH_SC3_PA3_FIFO_FULL                     = 0x000001a7,
PH_SC3_PA3_NULL_WE                       = 0x000001a8,
PH_SC3_PA3_EVENT_WE                      = 0x000001a9,
PH_SC3_PA3_FPOV_WE                       = 0x000001aa,
PH_SC3_PA3_LPOV_WE                       = 0x000001ab,
PH_SC3_PA3_EOP_WE                        = 0x000001ac,
PH_SC3_PA3_DATA_FIFO_EOP_RD              = 0x000001ad,
PH_SC3_PA3_EOPG_WE                       = 0x000001ae,
PH_SC3_PA3_DEALLOC_4_0_RD                = 0x000001af,
PH_SC3_PA4_DATA_FIFO_RD                  = 0x000001b0,
PH_SC3_PA4_DATA_FIFO_WE                  = 0x000001b1,
PH_SC3_PA4_FIFO_EMPTY                    = 0x000001b2,
PH_SC3_PA4_FIFO_FULL                     = 0x000001b3,
PH_SC3_PA4_NULL_WE                       = 0x000001b4,
PH_SC3_PA4_EVENT_WE                      = 0x000001b5,
PH_SC3_PA4_FPOV_WE                       = 0x000001b6,
PH_SC3_PA4_LPOV_WE                       = 0x000001b7,
PH_SC3_PA4_EOP_WE                        = 0x000001b8,
PH_SC3_PA4_DATA_FIFO_EOP_RD              = 0x000001b9,
PH_SC3_PA4_EOPG_WE                       = 0x000001ba,
PH_SC3_PA4_DEALLOC_4_0_RD                = 0x000001bb,
PH_SC3_PA5_DATA_FIFO_RD                  = 0x000001bc,
PH_SC3_PA5_DATA_FIFO_WE                  = 0x000001bd,
PH_SC3_PA5_FIFO_EMPTY                    = 0x000001be,
PH_SC3_PA5_FIFO_FULL                     = 0x000001bf,
PH_SC3_PA5_NULL_WE                       = 0x000001c0,
PH_SC3_PA5_EVENT_WE                      = 0x000001c1,
PH_SC3_PA5_FPOV_WE                       = 0x000001c2,
PH_SC3_PA5_LPOV_WE                       = 0x000001c3,
PH_SC3_PA5_EOP_WE                        = 0x000001c4,
PH_SC3_PA5_DATA_FIFO_EOP_RD              = 0x000001c5,
PH_SC3_PA5_EOPG_WE                       = 0x000001c6,
PH_SC3_PA5_DEALLOC_4_0_RD                = 0x000001c7,
PH_SC3_PA6_DATA_FIFO_RD                  = 0x000001c8,
PH_SC3_PA6_DATA_FIFO_WE                  = 0x000001c9,
PH_SC3_PA6_FIFO_EMPTY                    = 0x000001ca,
PH_SC3_PA6_FIFO_FULL                     = 0x000001cb,
PH_SC3_PA6_NULL_WE                       = 0x000001cc,
PH_SC3_PA6_EVENT_WE                      = 0x000001cd,
PH_SC3_PA6_FPOV_WE                       = 0x000001ce,
PH_SC3_PA6_LPOV_WE                       = 0x000001cf,
PH_SC3_PA6_EOP_WE                        = 0x000001d0,
PH_SC3_PA6_DATA_FIFO_EOP_RD              = 0x000001d1,
PH_SC3_PA6_EOPG_WE                       = 0x000001d2,
PH_SC3_PA6_DEALLOC_4_0_RD                = 0x000001d3,
PH_SC3_PA7_DATA_FIFO_RD                  = 0x000001d4,
PH_SC3_PA7_DATA_FIFO_WE                  = 0x000001d5,
PH_SC3_PA7_FIFO_EMPTY                    = 0x000001d6,
PH_SC3_PA7_FIFO_FULL                     = 0x000001d7,
PH_SC3_PA7_NULL_WE                       = 0x000001d8,
PH_SC3_PA7_EVENT_WE                      = 0x000001d9,
PH_SC3_PA7_FPOV_WE                       = 0x000001da,
PH_SC3_PA7_LPOV_WE                       = 0x000001db,
PH_SC3_PA7_EOP_WE                        = 0x000001dc,
PH_SC3_PA7_DATA_FIFO_EOP_RD              = 0x000001dd,
PH_SC3_PA7_EOPG_WE                       = 0x000001de,
PH_SC3_PA7_DEALLOC_4_0_RD                = 0x000001df,
PH_SC4_SRPS_WINDOW_VALID                 = 0x000001e0,
PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000001e1,
PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000001e2,
PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000001e3,
PH_SC4_ARB_STALLED_FROM_BELOW            = 0x000001e4,
PH_SC4_ARB_STARVED_FROM_ABOVE            = 0x000001e5,
PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6,
PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7,
PH_SC4_ARB_BUSY                          = 0x000001e8,
PH_SC4_ARB_PA_BUSY_SOP                   = 0x000001e9,
PH_SC4_ARB_EOP_POP_SYNC_POP              = 0x000001ea,
PH_SC4_ARB_EVENT_SYNC_POP                = 0x000001eb,
PH_SC4_PS_ENG_MULTICYCLE_BUBBLE          = 0x000001ec,
PH_SC4_EOP_SYNC_WINDOW                   = 0x000001ed,
PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000001ee,
PH_SC4_BUSY_CNT_NOT_ZERO                 = 0x000001ef,
PH_SC4_SEND                              = 0x000001f0,
PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000001f1,
PH_SC4_CREDIT_AT_MAX                     = 0x000001f2,
PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000001f3,
PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f4,
PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f5,
PH_SC4_GFX_PIPE0_TO_1_TRANSITION         = 0x000001f6,
PH_SC4_GFX_PIPE1_TO_0_TRANSITION         = 0x000001f7,
PH_SC4_PA0_DATA_FIFO_RD                  = 0x000001f8,
PH_SC4_PA0_DATA_FIFO_WE                  = 0x000001f9,
PH_SC4_PA0_FIFO_EMPTY                    = 0x000001fa,
PH_SC4_PA0_FIFO_FULL                     = 0x000001fb,
PH_SC4_PA0_NULL_WE                       = 0x000001fc,
PH_SC4_PA0_EVENT_WE                      = 0x000001fd,
PH_SC4_PA0_FPOV_WE                       = 0x000001fe,
PH_SC4_PA0_LPOV_WE                       = 0x000001ff,
PH_SC4_PA0_EOP_WE                        = 0x00000200,
PH_SC4_PA0_DATA_FIFO_EOP_RD              = 0x00000201,
PH_SC4_PA0_EOPG_WE                       = 0x00000202,
PH_SC4_PA0_DEALLOC_4_0_RD                = 0x00000203,
PH_SC4_PA1_DATA_FIFO_RD                  = 0x00000204,
PH_SC4_PA1_DATA_FIFO_WE                  = 0x00000205,
PH_SC4_PA1_FIFO_EMPTY                    = 0x00000206,
PH_SC4_PA1_FIFO_FULL                     = 0x00000207,
PH_SC4_PA1_NULL_WE                       = 0x00000208,
PH_SC4_PA1_EVENT_WE                      = 0x00000209,
PH_SC4_PA1_FPOV_WE                       = 0x0000020a,
PH_SC4_PA1_LPOV_WE                       = 0x0000020b,
PH_SC4_PA1_EOP_WE                        = 0x0000020c,
PH_SC4_PA1_DATA_FIFO_EOP_RD              = 0x0000020d,
PH_SC4_PA1_EOPG_WE                       = 0x0000020e,
PH_SC4_PA1_DEALLOC_4_0_RD                = 0x0000020f,
PH_SC4_PA2_DATA_FIFO_RD                  = 0x00000210,
PH_SC4_PA2_DATA_FIFO_WE                  = 0x00000211,
PH_SC4_PA2_FIFO_EMPTY                    = 0x00000212,
PH_SC4_PA2_FIFO_FULL                     = 0x00000213,
PH_SC4_PA2_NULL_WE                       = 0x00000214,
PH_SC4_PA2_EVENT_WE                      = 0x00000215,
PH_SC4_PA2_FPOV_WE                       = 0x00000216,
PH_SC4_PA2_LPOV_WE                       = 0x00000217,
PH_SC4_PA2_EOP_WE                        = 0x00000218,
PH_SC4_PA2_DATA_FIFO_EOP_RD              = 0x00000219,
PH_SC4_PA2_EOPG_WE                       = 0x0000021a,
PH_SC4_PA2_DEALLOC_4_0_RD                = 0x0000021b,
PH_SC4_PA3_DATA_FIFO_RD                  = 0x0000021c,
PH_SC4_PA3_DATA_FIFO_WE                  = 0x0000021d,
PH_SC4_PA3_FIFO_EMPTY                    = 0x0000021e,
PH_SC4_PA3_FIFO_FULL                     = 0x0000021f,
PH_SC4_PA3_NULL_WE                       = 0x00000220,
PH_SC4_PA3_EVENT_WE                      = 0x00000221,
PH_SC4_PA3_FPOV_WE                       = 0x00000222,
PH_SC4_PA3_LPOV_WE                       = 0x00000223,
PH_SC4_PA3_EOP_WE                        = 0x00000224,
PH_SC4_PA3_DATA_FIFO_EOP_RD              = 0x00000225,
PH_SC4_PA3_EOPG_WE                       = 0x00000226,
PH_SC4_PA3_DEALLOC_4_0_RD                = 0x00000227,
PH_SC4_PA4_DATA_FIFO_RD                  = 0x00000228,
PH_SC4_PA4_DATA_FIFO_WE                  = 0x00000229,
PH_SC4_PA4_FIFO_EMPTY                    = 0x0000022a,
PH_SC4_PA4_FIFO_FULL                     = 0x0000022b,
PH_SC4_PA4_NULL_WE                       = 0x0000022c,
PH_SC4_PA4_EVENT_WE                      = 0x0000022d,
PH_SC4_PA4_FPOV_WE                       = 0x0000022e,
PH_SC4_PA4_LPOV_WE                       = 0x0000022f,
PH_SC4_PA4_EOP_WE                        = 0x00000230,
PH_SC4_PA4_DATA_FIFO_EOP_RD              = 0x00000231,
PH_SC4_PA4_EOPG_WE                       = 0x00000232,
PH_SC4_PA4_DEALLOC_4_0_RD                = 0x00000233,
PH_SC4_PA5_DATA_FIFO_RD                  = 0x00000234,
PH_SC4_PA5_DATA_FIFO_WE                  = 0x00000235,
PH_SC4_PA5_FIFO_EMPTY                    = 0x00000236,
PH_SC4_PA5_FIFO_FULL                     = 0x00000237,
PH_SC4_PA5_NULL_WE                       = 0x00000238,
PH_SC4_PA5_EVENT_WE                      = 0x00000239,
PH_SC4_PA5_FPOV_WE                       = 0x0000023a,
PH_SC4_PA5_LPOV_WE                       = 0x0000023b,
PH_SC4_PA5_EOP_WE                        = 0x0000023c,
PH_SC4_PA5_DATA_FIFO_EOP_RD              = 0x0000023d,
PH_SC4_PA5_EOPG_WE                       = 0x0000023e,
PH_SC4_PA5_DEALLOC_4_0_RD                = 0x0000023f,
PH_SC4_PA6_DATA_FIFO_RD                  = 0x00000240,
PH_SC4_PA6_DATA_FIFO_WE                  = 0x00000241,
PH_SC4_PA6_FIFO_EMPTY                    = 0x00000242,
PH_SC4_PA6_FIFO_FULL                     = 0x00000243,
PH_SC4_PA6_NULL_WE                       = 0x00000244,
PH_SC4_PA6_EVENT_WE                      = 0x00000245,
PH_SC4_PA6_FPOV_WE                       = 0x00000246,
PH_SC4_PA6_LPOV_WE                       = 0x00000247,
PH_SC4_PA6_EOP_WE                        = 0x00000248,
PH_SC4_PA6_DATA_FIFO_EOP_RD              = 0x00000249,
PH_SC4_PA6_EOPG_WE                       = 0x0000024a,
PH_SC4_PA6_DEALLOC_4_0_RD                = 0x0000024b,
PH_SC4_PA7_DATA_FIFO_RD                  = 0x0000024c,
PH_SC4_PA7_DATA_FIFO_WE                  = 0x0000024d,
PH_SC4_PA7_FIFO_EMPTY                    = 0x0000024e,
PH_SC4_PA7_FIFO_FULL                     = 0x0000024f,
PH_SC4_PA7_NULL_WE                       = 0x00000250,
PH_SC4_PA7_EVENT_WE                      = 0x00000251,
PH_SC4_PA7_FPOV_WE                       = 0x00000252,
PH_SC4_PA7_LPOV_WE                       = 0x00000253,
PH_SC4_PA7_EOP_WE                        = 0x00000254,
PH_SC4_PA7_DATA_FIFO_EOP_RD              = 0x00000255,
PH_SC4_PA7_EOPG_WE                       = 0x00000256,
PH_SC4_PA7_DEALLOC_4_0_RD                = 0x00000257,
PH_SC5_SRPS_WINDOW_VALID                 = 0x00000258,
PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000259,
PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000025a,
PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000025b,
PH_SC5_ARB_STALLED_FROM_BELOW            = 0x0000025c,
PH_SC5_ARB_STARVED_FROM_ABOVE            = 0x0000025d,
PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e,
PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f,
PH_SC5_ARB_BUSY                          = 0x00000260,
PH_SC5_ARB_PA_BUSY_SOP                   = 0x00000261,
PH_SC5_ARB_EOP_POP_SYNC_POP              = 0x00000262,
PH_SC5_ARB_EVENT_SYNC_POP                = 0x00000263,
PH_SC5_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000264,
PH_SC5_EOP_SYNC_WINDOW                   = 0x00000265,
PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000266,
PH_SC5_BUSY_CNT_NOT_ZERO                 = 0x00000267,
PH_SC5_SEND                              = 0x00000268,
PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000269,
PH_SC5_CREDIT_AT_MAX                     = 0x0000026a,
PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000026b,
PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026c,
PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026d,
PH_SC5_GFX_PIPE0_TO_1_TRANSITION         = 0x0000026e,
PH_SC5_GFX_PIPE1_TO_0_TRANSITION         = 0x0000026f,
PH_SC5_PA0_DATA_FIFO_RD                  = 0x00000270,
PH_SC5_PA0_DATA_FIFO_WE                  = 0x00000271,
PH_SC5_PA0_FIFO_EMPTY                    = 0x00000272,
PH_SC5_PA0_FIFO_FULL                     = 0x00000273,
PH_SC5_PA0_NULL_WE                       = 0x00000274,
PH_SC5_PA0_EVENT_WE                      = 0x00000275,
PH_SC5_PA0_FPOV_WE                       = 0x00000276,
PH_SC5_PA0_LPOV_WE                       = 0x00000277,
PH_SC5_PA0_EOP_WE                        = 0x00000278,
PH_SC5_PA0_DATA_FIFO_EOP_RD              = 0x00000279,
PH_SC5_PA0_EOPG_WE                       = 0x0000027a,
PH_SC5_PA0_DEALLOC_4_0_RD                = 0x0000027b,
PH_SC5_PA1_DATA_FIFO_RD                  = 0x0000027c,
PH_SC5_PA1_DATA_FIFO_WE                  = 0x0000027d,
PH_SC5_PA1_FIFO_EMPTY                    = 0x0000027e,
PH_SC5_PA1_FIFO_FULL                     = 0x0000027f,
PH_SC5_PA1_NULL_WE                       = 0x00000280,
PH_SC5_PA1_EVENT_WE                      = 0x00000281,
PH_SC5_PA1_FPOV_WE                       = 0x00000282,
PH_SC5_PA1_LPOV_WE                       = 0x00000283,
PH_SC5_PA1_EOP_WE                        = 0x00000284,
PH_SC5_PA1_DATA_FIFO_EOP_RD              = 0x00000285,
PH_SC5_PA1_EOPG_WE                       = 0x00000286,
PH_SC5_PA1_DEALLOC_4_0_RD                = 0x00000287,
PH_SC5_PA2_DATA_FIFO_RD                  = 0x00000288,
PH_SC5_PA2_DATA_FIFO_WE                  = 0x00000289,
PH_SC5_PA2_FIFO_EMPTY                    = 0x0000028a,
PH_SC5_PA2_FIFO_FULL                     = 0x0000028b,
PH_SC5_PA2_NULL_WE                       = 0x0000028c,
PH_SC5_PA2_EVENT_WE                      = 0x0000028d,
PH_SC5_PA2_FPOV_WE                       = 0x0000028e,
PH_SC5_PA2_LPOV_WE                       = 0x0000028f,
PH_SC5_PA2_EOP_WE                        = 0x00000290,
PH_SC5_PA2_DATA_FIFO_EOP_RD              = 0x00000291,
PH_SC5_PA2_EOPG_WE                       = 0x00000292,
PH_SC5_PA2_DEALLOC_4_0_RD                = 0x00000293,
PH_SC5_PA3_DATA_FIFO_RD                  = 0x00000294,
PH_SC5_PA3_DATA_FIFO_WE                  = 0x00000295,
PH_SC5_PA3_FIFO_EMPTY                    = 0x00000296,
PH_SC5_PA3_FIFO_FULL                     = 0x00000297,
PH_SC5_PA3_NULL_WE                       = 0x00000298,
PH_SC5_PA3_EVENT_WE                      = 0x00000299,
PH_SC5_PA3_FPOV_WE                       = 0x0000029a,
PH_SC5_PA3_LPOV_WE                       = 0x0000029b,
PH_SC5_PA3_EOP_WE                        = 0x0000029c,
PH_SC5_PA3_DATA_FIFO_EOP_RD              = 0x0000029d,
PH_SC5_PA3_EOPG_WE                       = 0x0000029e,
PH_SC5_PA3_DEALLOC_4_0_RD                = 0x0000029f,
PH_SC5_PA4_DATA_FIFO_RD                  = 0x000002a0,
PH_SC5_PA4_DATA_FIFO_WE                  = 0x000002a1,
PH_SC5_PA4_FIFO_EMPTY                    = 0x000002a2,
PH_SC5_PA4_FIFO_FULL                     = 0x000002a3,
PH_SC5_PA4_NULL_WE                       = 0x000002a4,
PH_SC5_PA4_EVENT_WE                      = 0x000002a5,
PH_SC5_PA4_FPOV_WE                       = 0x000002a6,
PH_SC5_PA4_LPOV_WE                       = 0x000002a7,
PH_SC5_PA4_EOP_WE                        = 0x000002a8,
PH_SC5_PA4_DATA_FIFO_EOP_RD              = 0x000002a9,
PH_SC5_PA4_EOPG_WE                       = 0x000002aa,
PH_SC5_PA4_DEALLOC_4_0_RD                = 0x000002ab,
PH_SC5_PA5_DATA_FIFO_RD                  = 0x000002ac,
PH_SC5_PA5_DATA_FIFO_WE                  = 0x000002ad,
PH_SC5_PA5_FIFO_EMPTY                    = 0x000002ae,
PH_SC5_PA5_FIFO_FULL                     = 0x000002af,
PH_SC5_PA5_NULL_WE                       = 0x000002b0,
PH_SC5_PA5_EVENT_WE                      = 0x000002b1,
PH_SC5_PA5_FPOV_WE                       = 0x000002b2,
PH_SC5_PA5_LPOV_WE                       = 0x000002b3,
PH_SC5_PA5_EOP_WE                        = 0x000002b4,
PH_SC5_PA5_DATA_FIFO_EOP_RD              = 0x000002b5,
PH_SC5_PA5_EOPG_WE                       = 0x000002b6,
PH_SC5_PA5_DEALLOC_4_0_RD                = 0x000002b7,
PH_SC5_PA6_DATA_FIFO_RD                  = 0x000002b8,
PH_SC5_PA6_DATA_FIFO_WE                  = 0x000002b9,
PH_SC5_PA6_FIFO_EMPTY                    = 0x000002ba,
PH_SC5_PA6_FIFO_FULL                     = 0x000002bb,
PH_SC5_PA6_NULL_WE                       = 0x000002bc,
PH_SC5_PA6_EVENT_WE                      = 0x000002bd,
PH_SC5_PA6_FPOV_WE                       = 0x000002be,
PH_SC5_PA6_LPOV_WE                       = 0x000002bf,
PH_SC5_PA6_EOP_WE                        = 0x000002c0,
PH_SC5_PA6_DATA_FIFO_EOP_RD              = 0x000002c1,
PH_SC5_PA6_EOPG_WE                       = 0x000002c2,
PH_SC5_PA6_DEALLOC_4_0_RD                = 0x000002c3,
PH_SC5_PA7_DATA_FIFO_RD                  = 0x000002c4,
PH_SC5_PA7_DATA_FIFO_WE                  = 0x000002c5,
PH_SC5_PA7_FIFO_EMPTY                    = 0x000002c6,
PH_SC5_PA7_FIFO_FULL                     = 0x000002c7,
PH_SC5_PA7_NULL_WE                       = 0x000002c8,
PH_SC5_PA7_EVENT_WE                      = 0x000002c9,
PH_SC5_PA7_FPOV_WE                       = 0x000002ca,
PH_SC5_PA7_LPOV_WE                       = 0x000002cb,
PH_SC5_PA7_EOP_WE                        = 0x000002cc,
PH_SC5_PA7_DATA_FIFO_EOP_RD              = 0x000002cd,
PH_SC5_PA7_EOPG_WE                       = 0x000002ce,
PH_SC5_PA7_DEALLOC_4_0_RD                = 0x000002cf,
PH_SC6_SRPS_WINDOW_VALID                 = 0x000002d0,
PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x000002d1,
PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES          = 0x000002d2,
PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x000002d3,
PH_SC6_ARB_STALLED_FROM_BELOW            = 0x000002d4,
PH_SC6_ARB_STARVED_FROM_ABOVE            = 0x000002d5,
PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6,
PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7,
PH_SC6_ARB_BUSY                          = 0x000002d8,
PH_SC6_ARB_PA_BUSY_SOP                   = 0x000002d9,
PH_SC6_ARB_EOP_POP_SYNC_POP              = 0x000002da,
PH_SC6_ARB_EVENT_SYNC_POP                = 0x000002db,
PH_SC6_PS_ENG_MULTICYCLE_BUBBLE          = 0x000002dc,
PH_SC6_EOP_SYNC_WINDOW                   = 0x000002dd,
PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x000002de,
PH_SC6_BUSY_CNT_NOT_ZERO                 = 0x000002df,
PH_SC6_SEND                              = 0x000002e0,
PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x000002e1,
PH_SC6_CREDIT_AT_MAX                     = 0x000002e2,
PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x000002e3,
PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e4,
PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e5,
PH_SC6_GFX_PIPE0_TO_1_TRANSITION         = 0x000002e6,
PH_SC6_GFX_PIPE1_TO_0_TRANSITION         = 0x000002e7,
PH_SC6_PA0_DATA_FIFO_RD                  = 0x000002e8,
PH_SC6_PA0_DATA_FIFO_WE                  = 0x000002e9,
PH_SC6_PA0_FIFO_EMPTY                    = 0x000002ea,
PH_SC6_PA0_FIFO_FULL                     = 0x000002eb,
PH_SC6_PA0_NULL_WE                       = 0x000002ec,
PH_SC6_PA0_EVENT_WE                      = 0x000002ed,
PH_SC6_PA0_FPOV_WE                       = 0x000002ee,
PH_SC6_PA0_LPOV_WE                       = 0x000002ef,
PH_SC6_PA0_EOP_WE                        = 0x000002f0,
PH_SC6_PA0_DATA_FIFO_EOP_RD              = 0x000002f1,
PH_SC6_PA0_EOPG_WE                       = 0x000002f2,
PH_SC6_PA0_DEALLOC_4_0_RD                = 0x000002f3,
PH_SC6_PA1_DATA_FIFO_RD                  = 0x000002f4,
PH_SC6_PA1_DATA_FIFO_WE                  = 0x000002f5,
PH_SC6_PA1_FIFO_EMPTY                    = 0x000002f6,
PH_SC6_PA1_FIFO_FULL                     = 0x000002f7,
PH_SC6_PA1_NULL_WE                       = 0x000002f8,
PH_SC6_PA1_EVENT_WE                      = 0x000002f9,
PH_SC6_PA1_FPOV_WE                       = 0x000002fa,
PH_SC6_PA1_LPOV_WE                       = 0x000002fb,
PH_SC6_PA1_EOP_WE                        = 0x000002fc,
PH_SC6_PA1_DATA_FIFO_EOP_RD              = 0x000002fd,
PH_SC6_PA1_EOPG_WE                       = 0x000002fe,
PH_SC6_PA1_DEALLOC_4_0_RD                = 0x000002ff,
PH_SC6_PA2_DATA_FIFO_RD                  = 0x00000300,
PH_SC6_PA2_DATA_FIFO_WE                  = 0x00000301,
PH_SC6_PA2_FIFO_EMPTY                    = 0x00000302,
PH_SC6_PA2_FIFO_FULL                     = 0x00000303,
PH_SC6_PA2_NULL_WE                       = 0x00000304,
PH_SC6_PA2_EVENT_WE                      = 0x00000305,
PH_SC6_PA2_FPOV_WE                       = 0x00000306,
PH_SC6_PA2_LPOV_WE                       = 0x00000307,
PH_SC6_PA2_EOP_WE                        = 0x00000308,
PH_SC6_PA2_DATA_FIFO_EOP_RD              = 0x00000309,
PH_SC6_PA2_EOPG_WE                       = 0x0000030a,
PH_SC6_PA2_DEALLOC_4_0_RD                = 0x0000030b,
PH_SC6_PA3_DATA_FIFO_RD                  = 0x0000030c,
PH_SC6_PA3_DATA_FIFO_WE                  = 0x0000030d,
PH_SC6_PA3_FIFO_EMPTY                    = 0x0000030e,
PH_SC6_PA3_FIFO_FULL                     = 0x0000030f,
PH_SC6_PA3_NULL_WE                       = 0x00000310,
PH_SC6_PA3_EVENT_WE                      = 0x00000311,
PH_SC6_PA3_FPOV_WE                       = 0x00000312,
PH_SC6_PA3_LPOV_WE                       = 0x00000313,
PH_SC6_PA3_EOP_WE                        = 0x00000314,
PH_SC6_PA3_DATA_FIFO_EOP_RD              = 0x00000315,
PH_SC6_PA3_EOPG_WE                       = 0x00000316,
PH_SC6_PA3_DEALLOC_4_0_RD                = 0x00000317,
PH_SC6_PA4_DATA_FIFO_RD                  = 0x00000318,
PH_SC6_PA4_DATA_FIFO_WE                  = 0x00000319,
PH_SC6_PA4_FIFO_EMPTY                    = 0x0000031a,
PH_SC6_PA4_FIFO_FULL                     = 0x0000031b,
PH_SC6_PA4_NULL_WE                       = 0x0000031c,
PH_SC6_PA4_EVENT_WE                      = 0x0000031d,
PH_SC6_PA4_FPOV_WE                       = 0x0000031e,
PH_SC6_PA4_LPOV_WE                       = 0x0000031f,
PH_SC6_PA4_EOP_WE                        = 0x00000320,
PH_SC6_PA4_DATA_FIFO_EOP_RD              = 0x00000321,
PH_SC6_PA4_EOPG_WE                       = 0x00000322,
PH_SC6_PA4_DEALLOC_4_0_RD                = 0x00000323,
PH_SC6_PA5_DATA_FIFO_RD                  = 0x00000324,
PH_SC6_PA5_DATA_FIFO_WE                  = 0x00000325,
PH_SC6_PA5_FIFO_EMPTY                    = 0x00000326,
PH_SC6_PA5_FIFO_FULL                     = 0x00000327,
PH_SC6_PA5_NULL_WE                       = 0x00000328,
PH_SC6_PA5_EVENT_WE                      = 0x00000329,
PH_SC6_PA5_FPOV_WE                       = 0x0000032a,
PH_SC6_PA5_LPOV_WE                       = 0x0000032b,
PH_SC6_PA5_EOP_WE                        = 0x0000032c,
PH_SC6_PA5_DATA_FIFO_EOP_RD              = 0x0000032d,
PH_SC6_PA5_EOPG_WE                       = 0x0000032e,
PH_SC6_PA5_DEALLOC_4_0_RD                = 0x0000032f,
PH_SC6_PA6_DATA_FIFO_RD                  = 0x00000330,
PH_SC6_PA6_DATA_FIFO_WE                  = 0x00000331,
PH_SC6_PA6_FIFO_EMPTY                    = 0x00000332,
PH_SC6_PA6_FIFO_FULL                     = 0x00000333,
PH_SC6_PA6_NULL_WE                       = 0x00000334,
PH_SC6_PA6_EVENT_WE                      = 0x00000335,
PH_SC6_PA6_FPOV_WE                       = 0x00000336,
PH_SC6_PA6_LPOV_WE                       = 0x00000337,
PH_SC6_PA6_EOP_WE                        = 0x00000338,
PH_SC6_PA6_DATA_FIFO_EOP_RD              = 0x00000339,
PH_SC6_PA6_EOPG_WE                       = 0x0000033a,
PH_SC6_PA6_DEALLOC_4_0_RD                = 0x0000033b,
PH_SC6_PA7_DATA_FIFO_RD                  = 0x0000033c,
PH_SC6_PA7_DATA_FIFO_WE                  = 0x0000033d,
PH_SC6_PA7_FIFO_EMPTY                    = 0x0000033e,
PH_SC6_PA7_FIFO_FULL                     = 0x0000033f,
PH_SC6_PA7_NULL_WE                       = 0x00000340,
PH_SC6_PA7_EVENT_WE                      = 0x00000341,
PH_SC6_PA7_FPOV_WE                       = 0x00000342,
PH_SC6_PA7_LPOV_WE                       = 0x00000343,
PH_SC6_PA7_EOP_WE                        = 0x00000344,
PH_SC6_PA7_DATA_FIFO_EOP_RD              = 0x00000345,
PH_SC6_PA7_EOPG_WE                       = 0x00000346,
PH_SC6_PA7_DEALLOC_4_0_RD                = 0x00000347,
PH_SC7_SRPS_WINDOW_VALID                 = 0x00000348,
PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES  = 0x00000349,
PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES          = 0x0000034a,
PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM     = 0x0000034b,
PH_SC7_ARB_STALLED_FROM_BELOW            = 0x0000034c,
PH_SC7_ARB_STARVED_FROM_ABOVE            = 0x0000034d,
PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e,
PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f,
PH_SC7_ARB_BUSY                          = 0x00000350,
PH_SC7_ARB_PA_BUSY_SOP                   = 0x00000351,
PH_SC7_ARB_EOP_POP_SYNC_POP              = 0x00000352,
PH_SC7_ARB_EVENT_SYNC_POP                = 0x00000353,
PH_SC7_PS_ENG_MULTICYCLE_BUBBLE          = 0x00000354,
PH_SC7_EOP_SYNC_WINDOW                   = 0x00000355,
PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM   = 0x00000356,
PH_SC7_BUSY_CNT_NOT_ZERO                 = 0x00000357,
PH_SC7_SEND                              = 0x00000358,
PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND  = 0x00000359,
PH_SC7_CREDIT_AT_MAX                     = 0x0000035a,
PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND     = 0x0000035b,
PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035c,
PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035d,
PH_SC7_GFX_PIPE0_TO_1_TRANSITION         = 0x0000035e,
PH_SC7_GFX_PIPE1_TO_0_TRANSITION         = 0x0000035f,
PH_SC7_PA0_DATA_FIFO_RD                  = 0x00000360,
PH_SC7_PA0_DATA_FIFO_WE                  = 0x00000361,
PH_SC7_PA0_FIFO_EMPTY                    = 0x00000362,
PH_SC7_PA0_FIFO_FULL                     = 0x00000363,
PH_SC7_PA0_NULL_WE                       = 0x00000364,
PH_SC7_PA0_EVENT_WE                      = 0x00000365,
PH_SC7_PA0_FPOV_WE                       = 0x00000366,
PH_SC7_PA0_LPOV_WE                       = 0x00000367,
PH_SC7_PA0_EOP_WE                        = 0x00000368,
PH_SC7_PA0_DATA_FIFO_EOP_RD              = 0x00000369,
PH_SC7_PA0_EOPG_WE                       = 0x0000036a,
PH_SC7_PA0_DEALLOC_4_0_RD                = 0x0000036b,
PH_SC7_PA1_DATA_FIFO_RD                  = 0x0000036c,
PH_SC7_PA1_DATA_FIFO_WE                  = 0x0000036d,
PH_SC7_PA1_FIFO_EMPTY                    = 0x0000036e,
PH_SC7_PA1_FIFO_FULL                     = 0x0000036f,
PH_SC7_PA1_NULL_WE                       = 0x00000370,
PH_SC7_PA1_EVENT_WE                      = 0x00000371,
PH_SC7_PA1_FPOV_WE                       = 0x00000372,
PH_SC7_PA1_LPOV_WE                       = 0x00000373,
PH_SC7_PA1_EOP_WE                        = 0x00000374,
PH_SC7_PA1_DATA_FIFO_EOP_RD              = 0x00000375,
PH_SC7_PA1_EOPG_WE                       = 0x00000376,
PH_SC7_PA1_DEALLOC_4_0_RD                = 0x00000377,
PH_SC7_PA2_DATA_FIFO_RD                  = 0x00000378,
PH_SC7_PA2_DATA_FIFO_WE                  = 0x00000379,
PH_SC7_PA2_FIFO_EMPTY                    = 0x0000037a,
PH_SC7_PA2_FIFO_FULL                     = 0x0000037b,
PH_SC7_PA2_NULL_WE                       = 0x0000037c,
PH_SC7_PA2_EVENT_WE                      = 0x0000037d,
PH_SC7_PA2_FPOV_WE                       = 0x0000037e,
PH_SC7_PA2_LPOV_WE                       = 0x0000037f,
PH_SC7_PA2_EOP_WE                        = 0x00000380,
PH_SC7_PA2_DATA_FIFO_EOP_RD              = 0x00000381,
PH_SC7_PA2_EOPG_WE                       = 0x00000382,
PH_SC7_PA2_DEALLOC_4_0_RD                = 0x00000383,
PH_SC7_PA3_DATA_FIFO_RD                  = 0x00000384,
PH_SC7_PA3_DATA_FIFO_WE                  = 0x00000385,
PH_SC7_PA3_FIFO_EMPTY                    = 0x00000386,
PH_SC7_PA3_FIFO_FULL                     = 0x00000387,
PH_SC7_PA3_NULL_WE                       = 0x00000388,
PH_SC7_PA3_EVENT_WE                      = 0x00000389,
PH_SC7_PA3_FPOV_WE                       = 0x0000038a,
PH_SC7_PA3_LPOV_WE                       = 0x0000038b,
PH_SC7_PA3_EOP_WE                        = 0x0000038c,
PH_SC7_PA3_DATA_FIFO_EOP_RD              = 0x0000038d,
PH_SC7_PA3_EOPG_WE                       = 0x0000038e,
PH_SC7_PA3_DEALLOC_4_0_RD                = 0x0000038f,
PH_SC7_PA4_DATA_FIFO_RD                  = 0x00000390,
PH_SC7_PA4_DATA_FIFO_WE                  = 0x00000391,
PH_SC7_PA4_FIFO_EMPTY                    = 0x00000392,
PH_SC7_PA4_FIFO_FULL                     = 0x00000393,
PH_SC7_PA4_NULL_WE                       = 0x00000394,
PH_SC7_PA4_EVENT_WE                      = 0x00000395,
PH_SC7_PA4_FPOV_WE                       = 0x00000396,
PH_SC7_PA4_LPOV_WE                       = 0x00000397,
PH_SC7_PA4_EOP_WE                        = 0x00000398,
PH_SC7_PA4_DATA_FIFO_EOP_RD              = 0x00000399,
PH_SC7_PA4_EOPG_WE                       = 0x0000039a,
PH_SC7_PA4_DEALLOC_4_0_RD                = 0x0000039b,
PH_SC7_PA5_DATA_FIFO_RD                  = 0x0000039c,
PH_SC7_PA5_DATA_FIFO_WE                  = 0x0000039d,
PH_SC7_PA5_FIFO_EMPTY                    = 0x0000039e,
PH_SC7_PA5_FIFO_FULL                     = 0x0000039f,
PH_SC7_PA5_NULL_WE                       = 0x000003a0,
PH_SC7_PA5_EVENT_WE                      = 0x000003a1,
PH_SC7_PA5_FPOV_WE                       = 0x000003a2,
PH_SC7_PA5_LPOV_WE                       = 0x000003a3,
PH_SC7_PA5_EOP_WE                        = 0x000003a4,
PH_SC7_PA5_DATA_FIFO_EOP_RD              = 0x000003a5,
PH_SC7_PA5_EOPG_WE                       = 0x000003a6,
PH_SC7_PA5_DEALLOC_4_0_RD                = 0x000003a7,
PH_SC7_PA6_DATA_FIFO_RD                  = 0x000003a8,
PH_SC7_PA6_DATA_FIFO_WE                  = 0x000003a9,
PH_SC7_PA6_FIFO_EMPTY                    = 0x000003aa,
PH_SC7_PA6_FIFO_FULL                     = 0x000003ab,
PH_SC7_PA6_NULL_WE                       = 0x000003ac,
PH_SC7_PA6_EVENT_WE                      = 0x000003ad,
PH_SC7_PA6_FPOV_WE                       = 0x000003ae,
PH_SC7_PA6_LPOV_WE                       = 0x000003af,
PH_SC7_PA6_EOP_WE                        = 0x000003b0,
PH_SC7_PA6_DATA_FIFO_EOP_RD              = 0x000003b1,
PH_SC7_PA6_EOPG_WE                       = 0x000003b2,
PH_SC7_PA6_DEALLOC_4_0_RD                = 0x000003b3,
PH_SC7_PA7_DATA_FIFO_RD                  = 0x000003b4,
PH_SC7_PA7_DATA_FIFO_WE                  = 0x000003b5,
PH_SC7_PA7_FIFO_EMPTY                    = 0x000003b6,
PH_SC7_PA7_FIFO_FULL                     = 0x000003b7,
PH_SC7_PA7_NULL_WE                       = 0x000003b8,
PH_SC7_PA7_EVENT_WE                      = 0x000003b9,
PH_SC7_PA7_FPOV_WE                       = 0x000003ba,
PH_SC7_PA7_LPOV_WE                       = 0x000003bb,
PH_SC7_PA7_EOP_WE                        = 0x000003bc,
PH_SC7_PA7_DATA_FIFO_EOP_RD              = 0x000003bd,
PH_SC7_PA7_EOPG_WE                       = 0x000003be,
PH_SC7_PA7_DEALLOC_4_0_RD                = 0x000003bf,
} PH_PERFCNT_SEL;

typedef enum PIPE_COMPAT_LEVEL {
GEN_ZERO                                 = 0x00000000,
GEN_ONE                                  = 0x00000001,
GEN_TWO                                  = 0x00000002,
GEN_RESERVED                             = 0x00000003,
} PIPE_COMPAT_LEVEL;

typedef enum ReadPolicy {
CACHE_LRU_RD                             = 0x00000000,
CACHE_STREAM_RD                          = 0x00000001,
CACHE_NOA                                = 0x00000002,
RESERVED_RDPOLICY                        = 0x00000003,
} ReadPolicy;

typedef enum SH_MEM_RETRY_MODE {
SH_MEM_RETRY_MODE_ALL                    = 0x00000000,
SH_MEM_RETRY_MODE_WRITEATOMIC            = 0x00000001,
SH_MEM_RETRY_MODE_NONE                   = 0x00000002,
} SH_MEM_RETRY_MODE;

typedef enum SPI_LB_WAVES_SELECT {
HS_GS                                    = 0x00000000,
VS_PS                                    = 0x00000001,
CS_NA                                    = 0x00000002,
SPI_LB_WAVES_RSVD                        = 0x00000003,
} SPI_LB_WAVES_SELECT;

typedef enum SQ_OOB_SELECT {
SQ_OOB_INDEX_AND_OFFSET                  = 0x00000000,
SQ_OOB_INDEX_ONLY                        = 0x00000001,
SQ_OOB_NUM_RECORDS_0                     = 0x00000002,
SQ_OOB_COMPLETE                          = 0x00000003,
} SQ_OOB_SELECT;

typedef enum SQ_TT_MODE {
SQ_TT_MODE_OFF                           = 0x00000000,
SQ_TT_MODE_ON                            = 0x00000001,
SQ_TT_MODE_GLOBAL                        = 0x00000002,
SQ_TT_MODE_DETAIL                        = 0x00000003,
} SQ_TT_MODE;

typedef enum SQ_TT_RT_FREQ {
SQ_TT_RT_FREQ_NEVER                      = 0x00000000,
SQ_TT_RT_FREQ_1024_CLK                   = 0x00000001,
SQ_TT_RT_FREQ_4096_CLK                   = 0x00000002,
} SQ_TT_RT_FREQ;

typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD       = 0x00000000,
SQ_TT_INST_EXCLUDE_EXPGNT234             = 0x00000001,
} SQ_TT_TOKEN_MASK_INST_EXCLUDE;

typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
SQ_TT_TOKEN_MASK_SQDEC_BIT               = 0x00000001,
SQ_TT_TOKEN_MASK_SHDEC_BIT               = 0x00000002,
SQ_TT_TOKEN_MASK_GFXUDEC_BIT             = 0x00000004,
SQ_TT_TOKEN_MASK_COMP_BIT                = 0x00000008,
SQ_TT_TOKEN_MASK_CONTEXT_BIT             = 0x00000010,
SQ_TT_TOKEN_MASK_CONFIG_BIT              = 0x00000020,
SQ_TT_TOKEN_MASK_OTHER_BIT               = 0x00000040,
SQ_TT_TOKEN_MASK_READS_BIT               = 0x00000080,
} SQ_TT_TOKEN_MASK_REG_INCLUDE;

typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
SQ_TT_TOKEN_MASK_SQDEC_SHIFT             = 0x00000000,
SQ_TT_TOKEN_MASK_SHDEC_SHIFT             = 0x00000001,
SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT           = 0x00000002,
SQ_TT_TOKEN_MASK_COMP_SHIFT              = 0x00000003,
SQ_TT_TOKEN_MASK_CONTEXT_SHIFT           = 0x00000004,
SQ_TT_TOKEN_MASK_CONFIG_SHIFT            = 0x00000005,
SQ_TT_TOKEN_MASK_OTHER_SHIFT             = 0x00000006,
SQ_TT_TOKEN_MASK_READS_SHIFT             = 0x00000007,
} SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT;

typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT       = 0x00000000,
SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT        = 0x00000001,
SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT       = 0x00000002,
SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT        = 0x00000003,
SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT         = 0x00000004,
SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT      = 0x00000005,
SQ_TT_TOKEN_EXCLUDE_REG_SHIFT            = 0x00000006,
SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT          = 0x00000007,
SQ_TT_TOKEN_EXCLUDE_INST_SHIFT           = 0x00000008,
SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT        = 0x00000009,
SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT      = 0x0000000a,
SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT           = 0x0000000b,
} SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT;

typedef enum SQ_TT_UTIL_TIMER {
SQ_TT_UTIL_TIMER_100_CLK                 = 0x00000000,
SQ_TT_UTIL_TIMER_250_CLK                 = 0x00000001,
} SQ_TT_UTIL_TIMER;

typedef enum SQ_TT_WAVESTART_MODE {
SQ_TT_WAVESTART_MODE_SHORT               = 0x00000000,
SQ_TT_WAVESTART_MODE_ALLOC               = 0x00000001,
SQ_TT_WAVESTART_MODE_PBB_ID              = 0x00000002,
} SQ_TT_WAVESTART_MODE;

typedef enum SQ_TT_WTYPE_INCLUDE {
SQ_TT_WTYPE_INCLUDE_PS_BIT               = 0x00000001,
SQ_TT_WTYPE_INCLUDE_VS_BIT               = 0x00000002,
SQ_TT_WTYPE_INCLUDE_GS_BIT               = 0x00000004,
SQ_TT_WTYPE_INCLUDE_ES_BIT               = 0x00000008,
SQ_TT_WTYPE_INCLUDE_HS_BIT               = 0x00000010,
SQ_TT_WTYPE_INCLUDE_LS_BIT               = 0x00000020,
SQ_TT_WTYPE_INCLUDE_CS_BIT               = 0x00000040,
} SQ_TT_WTYPE_INCLUDE;

typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
SQ_TT_WTYPE_INCLUDE_PS_SHIFT             = 0x00000000,
SQ_TT_WTYPE_INCLUDE_VS_SHIFT             = 0x00000001,
SQ_TT_WTYPE_INCLUDE_GS_SHIFT             = 0x00000002,
SQ_TT_WTYPE_INCLUDE_ES_SHIFT             = 0x00000003,
SQ_TT_WTYPE_INCLUDE_HS_SHIFT             = 0x00000004,
SQ_TT_WTYPE_INCLUDE_LS_SHIFT             = 0x00000005,
SQ_TT_WTYPE_INCLUDE_CS_SHIFT             = 0x00000006,
} SQ_TT_WTYPE_INCLUDE_SHIFT;

typedef enum SQ_WATCH_MODES {
SQ_WATCH_MODE_READ                       = 0x00000000,
SQ_WATCH_MODE_NONREAD                    = 0x00000001,
SQ_WATCH_MODE_ATOMIC                     = 0x00000002,
SQ_WATCH_MODE_ALL                        = 0x00000003,
} SQ_WATCH_MODES;

typedef enum SQ_WAVE_SCHED_MODES {
SQ_WAVE_SCHED_MODE_NORMAL                = 0x00000000,
SQ_WAVE_SCHED_MODE_EXPERT                = 0x00000001,
SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST       = 0x00000002,
} SQ_WAVE_SCHED_MODES;

typedef enum ScUncertaintyRegionMode {
SC_HALF_LSB                              = 0x00000000,
SC_LSB_ONE_SIDED                         = 0x00000001,
SC_LSB_TWO_SIDED                         = 0x00000002,
} ScUncertaintyRegionMode;

typedef enum ScUncertaintyRegionMult {
SC_UR_1X                                 = 0x00000000,
SC_UR_2X                                 = 0x00000001,
SC_UR_4X                                 = 0x00000002,
SC_UR_8X                                 = 0x00000003,
} ScUncertaintyRegionMult;

typedef enum TA_TC_REQ_MODES {
TA_TC_REQ_MODE_BORDER                    = 0x00000000,
TA_TC_REQ_MODE_TEX2                      = 0x00000001,
TA_TC_REQ_MODE_TEX1                      = 0x00000002,
TA_TC_REQ_MODE_TEX0                      = 0x00000003,
TA_TC_REQ_MODE_NORMAL                    = 0x00000004,
TA_TC_REQ_MODE_DWORD                     = 0x00000005,
TA_TC_REQ_MODE_BYTE                      = 0x00000006,
TA_TC_REQ_MODE_BYTE_NV                   = 0x00000007,
} TA_TC_REQ_MODES;

typedef enum TCC_MTYPE {
MTYPE_NC                                 = 0x00000000,
MTYPE_WC                                 = 0x00000001,
MTYPE_CC                                 = 0x00000002,
} TCC_MTYPE;

typedef enum TCP_OPCODE_TYPE {
TCP_OPCODE_READ                          = 0x00000000,
TCP_OPCODE_WRITE                         = 0x00000001,
TCP_OPCODE_ATOMIC                        = 0x00000002,
TCP_OPCODE_INV                           = 0x00000003,
TCP_OPCODE_ATOMIC_CMPSWAP                = 0x00000004,
TCP_OPCODE_SAMPLER                       = 0x00000005,
TCP_OPCODE_LOAD                          = 0x00000006,
TCP_OPCODE_GATHERH                       = 0x00000007,
} TCP_OPCODE_TYPE;

typedef enum UTCL0FaultType {
UTCL0_XNACK_SUCCESS                      = 0x00000000,
UTCL0_XNACK_RETRY                        = 0x00000001,
UTCL0_XNACK_PRT                          = 0x00000002,
UTCL0_XNACK_NO_RETRY                     = 0x00000003,
} UTCL0FaultType;

typedef enum UTCL0RequestType {
UTCL0_TYPE_NORMAL                        = 0x00000000,
UTCL0_TYPE_SHOOTDOWN                     = 0x00000001,
UTCL0_TYPE_BYPASS                        = 0x00000002,
} UTCL0RequestType;

typedef enum UTCL1PerfSel {
UTCL1_PERF_SEL_NONE                      = 0x00000000,
UTCL1_PERF_SEL_REQS                      = 0x00000001,
UTCL1_PERF_SEL_HITS                      = 0x00000002,
UTCL1_PERF_SEL_MISSES                    = 0x00000003,
UTCL1_PERF_SEL_BYPASS_REQS               = 0x00000004,
UTCL1_PERF_SEL_HIT_INV_FILTER_REQS       = 0x00000005,
UTCL1_PERF_SEL_NUM_SMALLK_PAGES          = 0x00000006,
UTCL1_PERF_SEL_NUM_BIGK_PAGES            = 0x00000007,
UTCL1_PERF_SEL_TOTAL_UTCL2_REQS          = 0x00000008,
UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 0x00000009,
UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS    = 0x0000000a,
UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL       = 0x0000000b,
UTCL1_PERF_SEL_STALL_MH_CAM_FULL         = 0x0000000c,
UTCL1_PERF_SEL_NONRANGE_INV_REQS         = 0x0000000d,
UTCL1_PERF_SEL_RANGE_INV_REQS            = 0x0000000e,
} UTCL1PerfSel;

typedef enum VGT_DETECT_ONE {
ENABLE_TF1_OPT                           = 0x00000000,
DISABLE_TF1_OPT                          = 0x00000001,
} VGT_DETECT_ONE;

typedef enum VGT_DETECT_ZERO {
ENABLE_TF0_OPT                           = 0x00000000,
DISABLE_TF0_OPT                          = 0x00000001,
} VGT_DETECT_ZERO;

typedef enum VMEMCMD_RETURN_ORDER {
VMEMCMD_RETURN_OUT_OF_ORDER              = 0x00000000,
VMEMCMD_RETURN_IN_ORDER                  = 0x00000001,
VMEMCMD_RETURN_IN_ORDER_READ             = 0x00000002,
} VMEMCMD_RETURN_ORDER;

typedef enum WritePolicy {
CACHE_LRU_WR                             = 0x00000000,
CACHE_STREAM                             = 0x00000001,
CACHE_NOA_WR                             = 0x00000002,
CACHE_BYPASS                             = 0x00000003,
} WritePolicy;

//Merged Defines
#define CONFIG_SPACE1_END                               0x00002bff
#define CONFIG_SPACE1_START                             0x00002000
#define CONFIG_SPACE2_END                               0x00009fff
#define CONFIG_SPACE2_START                             0x00003000
#define CONFIG_SPACE_END                                0x00009fff
#define CONFIG_SPACE_START                              0x00002000
#define CONTEXT_SPACE_END                               0x0000bfff
#define CONTEXT_SPACE_START                             0x0000a000
#define CSDATA_ADDR_WIDTH                               0x00000007
#define CSDATA_DATA_WIDTH                               0x00000020
#define CSDATA_TYPE_WIDTH                               0x00000002
#define GB_TILING_CONFIG_MACROTABLE_SIZE                0x00000010
#define GB_TILING_CONFIG_TABLE_SIZE                     0x00000020
#define GSTHREADID_SIZE                                 0x00000002
#define INST_ID_ECC_INTERRUPT_MSG                       0xfffffff0
#define INST_ID_HOST_REG_TRAP_MSG                       0xfffffffe
#define INST_ID_HW_TRAP                                 0xfffffff2
#define INST_ID_KILL_SEQ                                0xfffffff3
#define INST_ID_PRIV_START                              0x80000000
#define INST_ID_SPI_WREXEC                              0xfffffff4
#define INST_ID_TTRACE_NEW_PC_MSG                       0xfffffff1
#define IQ_DEQUEUE_RETRY                                0x00000004
#define IQ_INTR_TYPE_IB                                 0x00000001
#define IQ_INTR_TYPE_MQD                                0x00000002
#define IQ_INTR_TYPE_PQ                                 0x00000000
#define IQ_OFFLOAD_RETRY                                0x00000001
#define IQ_QUEUE_SLEEP                                  0x00000000
#define IQ_SCH_WAVE_MSG                                 0x00000002
#define IQ_SEM_REARM                                    0x00000003
#define PERSISTENT_SPACE_END                            0x00002fff
#define PERSISTENT_SPACE_START                          0x00002c00
#define ROM_SIGNATURE                                   0x0000aa55
#define SEM_ECC_ERROR                                   0x00000000
#define SQDEC_BEGIN                                     0x00002300
#define SQDEC_END                                       0x000023ff
#define SQGFXUDEC_BEGIN                                 0x0000c330
#define SQGFXUDEC_END                                   0x0000c380
#define SQIND_GLOBAL_REGS_OFFSET                        0x00000000
#define SQIND_GLOBAL_REGS_SIZE                          0x00000008
#define SQIND_LOCAL_REGS_OFFSET                         0x00000008
#define SQIND_LOCAL_REGS_SIZE                           0x00000008
#define SQIND_WAVE_SGPRS_OFFSET                         0x00000200
#define SQIND_WAVE_SGPRS_SIZE                           0x00000200
#define SQPERFDDEC_BEGIN                                0x0000d1c0
#define SQPERFDDEC_END                                  0x0000d240
#define SQPERFSDEC_BEGIN                                0x0000d9c0
#define SQPERFSDEC_END                                  0x0000da40
#define SQPWRDEC_BEGIN                                  0x0000f08c
#define SQPWRDEC_END                                    0x0000f094
#define SQ_ATTR0__GFX09                                 0x00000000
#define SQ_BUFFER_ATOMIC_ADD__GFX09                     0x00000042
#define SQ_BUFFER_ATOMIC_ADD_X2__GFX09                  0x00000062
#define SQ_BUFFER_ATOMIC_AND__GFX09                     0x00000048
#define SQ_BUFFER_ATOMIC_AND_X2__GFX09                  0x00000068
#define SQ_BUFFER_ATOMIC_CMPSWAP__GFX09                 0x00000041
#define SQ_BUFFER_ATOMIC_CMPSWAP_X2__GFX09              0x00000061
#define SQ_BUFFER_ATOMIC_DEC__GFX09                     0x0000004c
#define SQ_BUFFER_ATOMIC_DEC_X2__GFX09                  0x0000006c
#define SQ_BUFFER_ATOMIC_INC__GFX09                     0x0000004b
#define SQ_BUFFER_ATOMIC_INC_X2__GFX09                  0x0000006b
#define SQ_BUFFER_ATOMIC_OR__GFX09                      0x00000049
#define SQ_BUFFER_ATOMIC_OR_X2__GFX09                   0x00000069
#define SQ_BUFFER_ATOMIC_SMAX__GFX09                    0x00000046
#define SQ_BUFFER_ATOMIC_SMAX_X2__GFX09                 0x00000066
#define SQ_BUFFER_ATOMIC_SMIN__GFX09                    0x00000044
#define SQ_BUFFER_ATOMIC_SMIN_X2__GFX09                 0x00000064
#define SQ_BUFFER_ATOMIC_SUB__GFX09                     0x00000043
#define SQ_BUFFER_ATOMIC_SUB_X2__GFX09                  0x00000063
#define SQ_BUFFER_ATOMIC_SWAP__GFX09                    0x00000040
#define SQ_BUFFER_ATOMIC_SWAP_X2__GFX09                 0x00000060
#define SQ_BUFFER_ATOMIC_UMAX__GFX09                    0x00000047
#define SQ_BUFFER_ATOMIC_UMAX_X2__GFX09                 0x00000067
#define SQ_BUFFER_ATOMIC_UMIN__GFX09                    0x00000045
#define SQ_BUFFER_ATOMIC_UMIN_X2__GFX09                 0x00000065
#define SQ_BUFFER_ATOMIC_XOR__GFX09                     0x0000004a
#define SQ_BUFFER_ATOMIC_XOR_X2__GFX09                  0x0000006a
#define SQ_BUFFER_LOAD_DWORD__GFX09                     0x00000014
#define SQ_BUFFER_LOAD_DWORDX2__GFX09                   0x00000015
#define SQ_BUFFER_LOAD_DWORDX3__GFX09                   0x00000016
#define SQ_BUFFER_LOAD_DWORDX4__GFX09                   0x00000017
#define SQ_BUFFER_LOAD_FORMAT_D16_X__GFX09              0x00000008
#define SQ_BUFFER_LOAD_FORMAT_D16_XY__GFX09             0x00000009
#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ__GFX09            0x0000000a
#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW__GFX09           0x0000000b
#define SQ_BUFFER_LOAD_FORMAT_X__GFX09                  0x00000000
#define SQ_BUFFER_LOAD_FORMAT_XY__GFX09                 0x00000001
#define SQ_BUFFER_LOAD_FORMAT_XYZ__GFX09                0x00000002
#define SQ_BUFFER_LOAD_FORMAT_XYZW__GFX09               0x00000003
#define SQ_BUFFER_LOAD_SBYTE__GFX09                     0x00000011
#define SQ_BUFFER_LOAD_SSHORT__GFX09                    0x00000013
#define SQ_BUFFER_LOAD_UBYTE__GFX09                     0x00000010
#define SQ_BUFFER_LOAD_USHORT__GFX09                    0x00000012
#define SQ_BUFFER_STORE_BYTE__GFX09                     0x00000018
#define SQ_BUFFER_STORE_DWORD__GFX09                    0x0000001c
#define SQ_BUFFER_STORE_DWORDX2__GFX09                  0x0000001d
#define SQ_BUFFER_STORE_DWORDX3__GFX09                  0x0000001e
#define SQ_BUFFER_STORE_DWORDX4__GFX09                  0x0000001f
#define SQ_BUFFER_STORE_FORMAT_D16_X__GFX09             0x0000000c
#define SQ_BUFFER_STORE_FORMAT_D16_XY__GFX09            0x0000000d
#define SQ_BUFFER_STORE_FORMAT_D16_XYZ__GFX09           0x0000000e
#define SQ_BUFFER_STORE_FORMAT_D16_XYZW__GFX09          0x0000000f
#define SQ_BUFFER_STORE_FORMAT_X__GFX09                 0x00000004
#define SQ_BUFFER_STORE_FORMAT_XY__GFX09                0x00000005
#define SQ_BUFFER_STORE_FORMAT_XYZ__GFX09               0x00000006
#define SQ_BUFFER_STORE_FORMAT_XYZW__GFX09              0x00000007
#define SQ_BUFFER_STORE_LDS_DWORD__GFX09                0x0000003d
#define SQ_BUFFER_STORE_SHORT__GFX09                    0x0000001a
#define SQ_BUFFER_WBINVL1__GFX09                        0x0000003e
#define SQ_BUFFER_WBINVL1_VOL__GFX09                    0x0000003f
#define SQ_CHAN_W__GFX09                                0x00000003
#define SQ_CHAN_X__GFX09                                0x00000000
#define SQ_CHAN_Y__GFX09                                0x00000001
#define SQ_CHAN_Z__GFX09                                0x00000002
#define SQ_CNT1__GFX09                                  0x00000000
#define SQ_CNT2__GFX09                                  0x00000001
#define SQ_CNT3__GFX09                                  0x00000002
#define SQ_CNT4__GFX09                                  0x00000003
#define SQ_DISPATCHER_GFX_CNT_PER_RING                  0x00000008
#define SQ_DISPATCHER_GFX_MIN                           0x00000010
#define SQ_DPP_BOUND_OFF__GFX09                         0x00000000
#define SQ_DPP_BOUND_ZERO__GFX09                        0x00000001
#define SQ_DPP_QUAD_PERM__GFX09                         0x00000000
#define SQ_DPP_ROW_BCAST15__GFX09                       0x00000142
#define SQ_DPP_ROW_BCAST31__GFX09                       0x00000143
#define SQ_DPP_ROW_HALF_MIRROR__GFX09                   0x00000141
#define SQ_DPP_ROW_MIRROR__GFX09                        0x00000140
#define SQ_DPP_ROW_RR1__GFX09                           0x00000121
#define SQ_DPP_ROW_RR10__GFX09                          0x0000012a
#define SQ_DPP_ROW_RR11__GFX09                          0x0000012b
#define SQ_DPP_ROW_RR12__GFX09                          0x0000012c
#define SQ_DPP_ROW_RR13__GFX09                          0x0000012d
#define SQ_DPP_ROW_RR14__GFX09                          0x0000012e
#define SQ_DPP_ROW_RR15__GFX09                          0x0000012f
#define SQ_DPP_ROW_RR2__GFX09                           0x00000122
#define SQ_DPP_ROW_RR3__GFX09                           0x00000123
#define SQ_DPP_ROW_RR4__GFX09                           0x00000124
#define SQ_DPP_ROW_RR5__GFX09                           0x00000125
#define SQ_DPP_ROW_RR6__GFX09                           0x00000126
#define SQ_DPP_ROW_RR7__GFX09                           0x00000127
#define SQ_DPP_ROW_RR8__GFX09                           0x00000128
#define SQ_DPP_ROW_RR9__GFX09                           0x00000129
#define SQ_DPP_ROW_SL1__GFX09                           0x00000101
#define SQ_DPP_ROW_SL10__GFX09                          0x0000010a
#define SQ_DPP_ROW_SL11__GFX09                          0x0000010b
#define SQ_DPP_ROW_SL12__GFX09                          0x0000010c
#define SQ_DPP_ROW_SL13__GFX09                          0x0000010d
#define SQ_DPP_ROW_SL14__GFX09                          0x0000010e
#define SQ_DPP_ROW_SL15__GFX09                          0x0000010f
#define SQ_DPP_ROW_SL2__GFX09                           0x00000102
#define SQ_DPP_ROW_SL3__GFX09                           0x00000103
#define SQ_DPP_ROW_SL4__GFX09                           0x00000104
#define SQ_DPP_ROW_SL5__GFX09                           0x00000105
#define SQ_DPP_ROW_SL6__GFX09                           0x00000106
#define SQ_DPP_ROW_SL7__GFX09                           0x00000107
#define SQ_DPP_ROW_SL8__GFX09                           0x00000108
#define SQ_DPP_ROW_SL9__GFX09                           0x00000109
#define SQ_DPP_ROW_SR1__GFX09                           0x00000111
#define SQ_DPP_ROW_SR10__GFX09                          0x0000011a
#define SQ_DPP_ROW_SR11__GFX09                          0x0000011b
#define SQ_DPP_ROW_SR12__GFX09                          0x0000011c
#define SQ_DPP_ROW_SR13__GFX09                          0x0000011d
#define SQ_DPP_ROW_SR14__GFX09                          0x0000011e
#define SQ_DPP_ROW_SR15__GFX09                          0x0000011f
#define SQ_DPP_ROW_SR2__GFX09                           0x00000112
#define SQ_DPP_ROW_SR3__GFX09                           0x00000113
#define SQ_DPP_ROW_SR4__GFX09                           0x00000114
#define SQ_DPP_ROW_SR5__GFX09                           0x00000115
#define SQ_DPP_ROW_SR6__GFX09                           0x00000116
#define SQ_DPP_ROW_SR7__GFX09                           0x00000117
#define SQ_DPP_ROW_SR8__GFX09                           0x00000118
#define SQ_DPP_ROW_SR9__GFX09                           0x00000119
#define SQ_DPP_WF_RL1__GFX09                            0x00000134
#define SQ_DPP_WF_RR1__GFX09                            0x0000013c
#define SQ_DPP_WF_SL1__GFX09                            0x00000130
#define SQ_DPP_WF_SR1__GFX09                            0x00000138
#define SQ_DS_ADD_F32__GFX09                            0x00000015
#define SQ_DS_ADD_RTN_F32__GFX09                        0x00000035
#define SQ_DS_ADD_RTN_U32__GFX09                        0x00000020
#define SQ_DS_ADD_RTN_U64__GFX09                        0x00000060
#define SQ_DS_ADD_SRC2_F32__GFX09                       0x00000095
#define SQ_DS_ADD_SRC2_U32__GFX09                       0x00000080
#define SQ_DS_ADD_SRC2_U64__GFX09                       0x000000c0
#define SQ_DS_ADD_U32__GFX09                            0x00000000
#define SQ_DS_ADD_U64__GFX09                            0x00000040
#define SQ_DS_AND_B32__GFX09                            0x00000009
#define SQ_DS_AND_B64__GFX09                            0x00000049
#define SQ_DS_AND_RTN_B32__GFX09                        0x00000029
#define SQ_DS_AND_RTN_B64__GFX09                        0x00000069
#define SQ_DS_AND_SRC2_B32__GFX09                       0x00000089
#define SQ_DS_AND_SRC2_B64__GFX09                       0x000000c9
#define SQ_DS_APPEND__GFX09                             0x000000be
#define SQ_DS_BPERMUTE_B32__GFX09                       0x0000003f
#define SQ_DS_CMPST_B32__GFX09                          0x00000010
#define SQ_DS_CMPST_B64__GFX09                          0x00000050
#define SQ_DS_CMPST_F32__GFX09                          0x00000011
#define SQ_DS_CMPST_F64__GFX09                          0x00000051
#define SQ_DS_CMPST_RTN_B32__GFX09                      0x00000030
#define SQ_DS_CMPST_RTN_B64__GFX09                      0x00000070
#define SQ_DS_CMPST_RTN_F32__GFX09                      0x00000031
#define SQ_DS_CMPST_RTN_F64__GFX09                      0x00000071
#define SQ_DS_CONDXCHG32_RTN_B128__GFX09                0x000000fd
#define SQ_DS_CONDXCHG32_RTN_B64__GFX09                 0x0000007e
#define SQ_DS_CONSUME__GFX09                            0x000000bd
#define SQ_DS_DEC_RTN_U32__GFX09                        0x00000024
#define SQ_DS_DEC_RTN_U64__GFX09                        0x00000064
#define SQ_DS_DEC_SRC2_U32__GFX09                       0x00000084
#define SQ_DS_DEC_SRC2_U64__GFX09                       0x000000c4
#define SQ_DS_DEC_U32__GFX09                            0x00000004
#define SQ_DS_DEC_U64__GFX09                            0x00000044
#define SQ_DS_GWS_BARRIER__GFX09                        0x0000009d
#define SQ_DS_GWS_INIT__GFX09                           0x00000099
#define SQ_DS_GWS_SEMA_BR__GFX09                        0x0000009b
#define SQ_DS_GWS_SEMA_P__GFX09                         0x0000009c
#define SQ_DS_GWS_SEMA_RELEASE_ALL__GFX09               0x00000098
#define SQ_DS_GWS_SEMA_V__GFX09                         0x0000009a
#define SQ_DS_INC_RTN_U32__GFX09                        0x00000023
#define SQ_DS_INC_RTN_U64__GFX09                        0x00000063
#define SQ_DS_INC_SRC2_U32__GFX09                       0x00000083
#define SQ_DS_INC_SRC2_U64__GFX09                       0x000000c3
#define SQ_DS_INC_U32__GFX09                            0x00000003
#define SQ_DS_INC_U64__GFX09                            0x00000043
#define SQ_DS_MAX_F32__GFX09                            0x00000013
#define SQ_DS_MAX_F64__GFX09                            0x00000053
#define SQ_DS_MAX_I32__GFX09                            0x00000006
#define SQ_DS_MAX_I64__GFX09                            0x00000046
#define SQ_DS_MAX_RTN_F32__GFX09                        0x00000033
#define SQ_DS_MAX_RTN_F64__GFX09                        0x00000073
#define SQ_DS_MAX_RTN_I32__GFX09                        0x00000026
#define SQ_DS_MAX_RTN_I64__GFX09                        0x00000066
#define SQ_DS_MAX_RTN_U32__GFX09                        0x00000028
#define SQ_DS_MAX_RTN_U64__GFX09                        0x00000068
#define SQ_DS_MAX_SRC2_F32__GFX09                       0x00000093
#define SQ_DS_MAX_SRC2_F64__GFX09                       0x000000d3
#define SQ_DS_MAX_SRC2_I32__GFX09                       0x00000086
#define SQ_DS_MAX_SRC2_I64__GFX09                       0x000000c6
#define SQ_DS_MAX_SRC2_U32__GFX09                       0x00000088
#define SQ_DS_MAX_SRC2_U64__GFX09                       0x000000c8
#define SQ_DS_MAX_U32__GFX09                            0x00000008
#define SQ_DS_MAX_U64__GFX09                            0x00000048
#define SQ_DS_MIN_F32__GFX09                            0x00000012
#define SQ_DS_MIN_F64__GFX09                            0x00000052
#define SQ_DS_MIN_I32__GFX09                            0x00000005
#define SQ_DS_MIN_I64__GFX09                            0x00000045
#define SQ_DS_MIN_RTN_F32__GFX09                        0x00000032
#define SQ_DS_MIN_RTN_F64__GFX09                        0x00000072
#define SQ_DS_MIN_RTN_I32__GFX09                        0x00000025
#define SQ_DS_MIN_RTN_I64__GFX09                        0x00000065
#define SQ_DS_MIN_RTN_U32__GFX09                        0x00000027
#define SQ_DS_MIN_RTN_U64__GFX09                        0x00000067
#define SQ_DS_MIN_SRC2_F32__GFX09                       0x00000092
#define SQ_DS_MIN_SRC2_F64__GFX09                       0x000000d2
#define SQ_DS_MIN_SRC2_I32__GFX09                       0x00000085
#define SQ_DS_MIN_SRC2_I64__GFX09                       0x000000c5
#define SQ_DS_MIN_SRC2_U32__GFX09                       0x00000087
#define SQ_DS_MIN_SRC2_U64__GFX09                       0x000000c7
#define SQ_DS_MIN_U32__GFX09                            0x00000007
#define SQ_DS_MIN_U64__GFX09                            0x00000047
#define SQ_DS_MSKOR_B32__GFX09                          0x0000000c
#define SQ_DS_MSKOR_B64__GFX09                          0x0000004c
#define SQ_DS_MSKOR_RTN_B32__GFX09                      0x0000002c
#define SQ_DS_MSKOR_RTN_B64__GFX09                      0x0000006c
#define SQ_DS_NOP__GFX09                                0x00000014
#define SQ_DS_ORDERED_COUNT__GFX09                      0x000000bf
#define SQ_DS_OR_B32__GFX09                             0x0000000a
#define SQ_DS_OR_B64__GFX09                             0x0000004a
#define SQ_DS_OR_RTN_B32__GFX09                         0x0000002a
#define SQ_DS_OR_RTN_B64__GFX09                         0x0000006a
#define SQ_DS_OR_SRC2_B32__GFX09                        0x0000008a
#define SQ_DS_OR_SRC2_B64__GFX09                        0x000000ca
#define SQ_DS_PERMUTE_B32__GFX09                        0x0000003e
#define SQ_DS_READ2ST64_B32__GFX09                      0x00000038
#define SQ_DS_READ2ST64_B64__GFX09                      0x00000078
#define SQ_DS_READ2_B32__GFX09                          0x00000037
#define SQ_DS_READ2_B64__GFX09                          0x00000077
#define SQ_DS_READ_B128__GFX09                          0x000000ff
#define SQ_DS_READ_B32__GFX09                           0x00000036
#define SQ_DS_READ_B64__GFX09                           0x00000076
#define SQ_DS_READ_B96__GFX09                           0x000000fe
#define SQ_DS_READ_I16__GFX09                           0x0000003b
#define SQ_DS_READ_I8__GFX09                            0x00000039
#define SQ_DS_READ_U16__GFX09                           0x0000003c
#define SQ_DS_READ_U8__GFX09                            0x0000003a
#define SQ_DS_RSUB_RTN_U32__GFX09                       0x00000022
#define SQ_DS_RSUB_RTN_U64__GFX09                       0x00000062
#define SQ_DS_RSUB_SRC2_U32__GFX09                      0x00000082
#define SQ_DS_RSUB_SRC2_U64__GFX09                      0x000000c2
#define SQ_DS_RSUB_U32__GFX09                           0x00000002
#define SQ_DS_RSUB_U64__GFX09                           0x00000042
#define SQ_DS_SUB_RTN_U32__GFX09                        0x00000021
#define SQ_DS_SUB_RTN_U64__GFX09                        0x00000061
#define SQ_DS_SUB_SRC2_U32__GFX09                       0x00000081
#define SQ_DS_SUB_SRC2_U64__GFX09                       0x000000c1
#define SQ_DS_SUB_U32__GFX09                            0x00000001
#define SQ_DS_SUB_U64__GFX09                            0x00000041
#define SQ_DS_SWIZZLE_B32__GFX09                        0x0000003d
#define SQ_DS_WRAP_RTN_B32__GFX09                       0x00000034
#define SQ_DS_WRITE2ST64_B32__GFX09                     0x0000000f
#define SQ_DS_WRITE2ST64_B64__GFX09                     0x0000004f
#define SQ_DS_WRITE2_B32__GFX09                         0x0000000e
#define SQ_DS_WRITE2_B64__GFX09                         0x0000004e
#define SQ_DS_WRITE_B128__GFX09                         0x000000df
#define SQ_DS_WRITE_B16__GFX09                          0x0000001f
#define SQ_DS_WRITE_B32__GFX09                          0x0000000d
#define SQ_DS_WRITE_B64__GFX09                          0x0000004d
#define SQ_DS_WRITE_B8__GFX09                           0x0000001e
#define SQ_DS_WRITE_B96__GFX09                          0x000000de
#define SQ_DS_WRITE_SRC2_B32__GFX09                     0x0000008d
#define SQ_DS_WRITE_SRC2_B64__GFX09                     0x000000cd
#define SQ_DS_WRXCHG2ST64_RTN_B32__GFX09                0x0000002f
#define SQ_DS_WRXCHG2ST64_RTN_B64__GFX09                0x0000006f
#define SQ_DS_WRXCHG2_RTN_B32__GFX09                    0x0000002e
#define SQ_DS_WRXCHG2_RTN_B64__GFX09                    0x0000006e
#define SQ_DS_WRXCHG_RTN_B32__GFX09                     0x0000002d
#define SQ_DS_WRXCHG_RTN_B64__GFX09                     0x0000006d
#define SQ_DS_XOR_B32__GFX09                            0x0000000b
#define SQ_DS_XOR_B64__GFX09                            0x0000004b
#define SQ_DS_XOR_RTN_B32__GFX09                        0x0000002b
#define SQ_DS_XOR_RTN_B64__GFX09                        0x0000006b
#define SQ_DS_XOR_SRC2_B32__GFX09                       0x0000008b
#define SQ_DS_XOR_SRC2_B64__GFX09                       0x000000cb
#define SQ_ENC_DS_BITS__GFX09                           0xd8000000
#define SQ_ENC_DS_FIELD__GFX09                          0x00000036
#define SQ_ENC_DS_MASK__GFX09                           0xfc000000
#define SQ_ENC_EXP_BITS__GFX09                          0xc4000000
#define SQ_ENC_EXP_FIELD__GFX09                         0x00000031
#define SQ_ENC_EXP_MASK__GFX09                          0xfc000000
#define SQ_ENC_FLAT_BITS__GFX09                         0xdc000000
#define SQ_ENC_FLAT_FIELD__GFX09                        0x00000037
#define SQ_ENC_FLAT_MASK__GFX09                         0xfc000000
#define SQ_ENC_MIMG_BITS__GFX09                         0xf0000000
#define SQ_ENC_MIMG_FIELD__GFX09                        0x0000003c
#define SQ_ENC_MIMG_MASK__GFX09                         0xfc000000
#define SQ_ENC_MTBUF_BITS__GFX09                        0xe8000000
#define SQ_ENC_MTBUF_FIELD__GFX09                       0x0000003a
#define SQ_ENC_MTBUF_MASK__GFX09                        0xfc000000
#define SQ_ENC_MUBUF_BITS__GFX09                        0xe0000000
#define SQ_ENC_MUBUF_FIELD__GFX09                       0x00000038
#define SQ_ENC_MUBUF_MASK__GFX09                        0xfc000000
#define SQ_ENC_SMEM_BITS__GFX09                         0xc0000000
#define SQ_ENC_SMEM_FIELD__GFX09                        0x00000030
#define SQ_ENC_SMEM_MASK__GFX09                         0xfc000000
#define SQ_ENC_SOP1_BITS__GFX09                         0xbe800000
#define SQ_ENC_SOP1_FIELD__GFX09                        0x0000017d
#define SQ_ENC_SOP1_MASK__GFX09                         0xff800000
#define SQ_ENC_SOP2_BITS__GFX09                         0x80000000
#define SQ_ENC_SOP2_FIELD__GFX09                        0x00000002
#define SQ_ENC_SOP2_MASK__GFX09                         0xc0000000
#define SQ_ENC_SOPC_BITS__GFX09                         0xbf000000
#define SQ_ENC_SOPC_FIELD__GFX09                        0x0000017e
#define SQ_ENC_SOPC_MASK__GFX09                         0xff800000
#define SQ_ENC_SOPK_BITS__GFX09                         0xb0000000
#define SQ_ENC_SOPK_FIELD__GFX09                        0x0000000b
#define SQ_ENC_SOPK_MASK__GFX09                         0xf0000000
#define SQ_ENC_SOPP_BITS__GFX09                         0xbf800000
#define SQ_ENC_SOPP_FIELD__GFX09                        0x0000017f
#define SQ_ENC_SOPP_MASK__GFX09                         0xff800000
#define SQ_ENC_VINTRP_BITS__GFX09                       0xd4000000
#define SQ_ENC_VINTRP_FIELD__GFX09                      0x00000035
#define SQ_ENC_VINTRP_MASK__GFX09                       0xfc000000
#define SQ_ENC_VOP1_BITS__GFX09                         0x7e000000
#define SQ_ENC_VOP1_FIELD__GFX09                        0x0000003f
#define SQ_ENC_VOP1_MASK__GFX09                         0xfe000000
#define SQ_ENC_VOP2_BITS__GFX09                         0x00000000
#define SQ_ENC_VOP2_FIELD__GFX09                        0x00000000
#define SQ_ENC_VOP2_MASK__GFX09                         0x80000000
#define SQ_ENC_VOP3_BITS__GFX09                         0xd0000000
#define SQ_ENC_VOP3_FIELD__GFX09                        0x00000034
#define SQ_ENC_VOP3_MASK__GFX09                         0xfc000000
#define SQ_ENC_VOPC_BITS__GFX09                         0x7c000000
#define SQ_ENC_VOPC_FIELD__GFX09                        0x0000003e
#define SQ_ENC_VOPC_MASK__GFX09                         0xfe000000
#define SQ_EQ__GFX09                                    0x00000002
#define SQ_EXEC_HI__GFX09                               0x0000007f
#define SQ_EXEC_LO__GFX09                               0x0000007e
#define SQ_EXP__GFX09                                   0x00000000
#define SQ_EXP_GDS0__GFX09                              0x00000018
#define SQ_EXP_MRT0__GFX09                              0x00000000
#define SQ_EXP_MRTZ__GFX09                              0x00000008
#define SQ_EXP_NULL__GFX09                              0x00000009
#define SQ_EXP_NUM_GDS__GFX09                           0x00000005
#define SQ_EXP_NUM_MRT__GFX09                           0x00000008
#define SQ_EXP_NUM_PARAM__GFX09                         0x00000020
#define SQ_EXP_NUM_POS__GFX09                           0x00000004
#define SQ_EXP_PARAM0__GFX09                            0x00000020
#define SQ_EXP_POS0__GFX09                              0x0000000c
#define SQ_EX_MODE_EXCP_DIV0                            0x00000002
#define SQ_EX_MODE_EXCP_INEXACT                         0x00000005
#define SQ_EX_MODE_EXCP_INPUT_DENORM                    0x00000001
#define SQ_EX_MODE_EXCP_INT_DIV0                        0x00000006
#define SQ_EX_MODE_EXCP_INVALID                         0x00000000
#define SQ_EX_MODE_EXCP_MEM_VIOL                        0x00000008
#define SQ_EX_MODE_EXCP_OVERFLOW                        0x00000003
#define SQ_EX_MODE_EXCP_UNDERFLOW                       0x00000004
#define SQ_EX_MODE_EXCP_VALU_BASE                       0x00000000
#define SQ_EX_MODE_EXCP_VALU_SIZE                       0x00000007
#define SQ_F__GFX09                                     0x00000000
#define SQ_FLAT__GFX09                                  0x00000000
#define SQ_FLAT_ATOMIC_ADD__GFX09                       0x00000042
#define SQ_FLAT_ATOMIC_ADD_X2__GFX09                    0x00000062
#define SQ_FLAT_ATOMIC_AND__GFX09                       0x00000048
#define SQ_FLAT_ATOMIC_AND_X2__GFX09                    0x00000068
#define SQ_FLAT_ATOMIC_CMPSWAP__GFX09                   0x00000041
#define SQ_FLAT_ATOMIC_CMPSWAP_X2__GFX09                0x00000061
#define SQ_FLAT_ATOMIC_DEC__GFX09                       0x0000004c
#define SQ_FLAT_ATOMIC_DEC_X2__GFX09                    0x0000006c
#define SQ_FLAT_ATOMIC_INC__GFX09                       0x0000004b
#define SQ_FLAT_ATOMIC_INC_X2__GFX09                    0x0000006b
#define SQ_FLAT_ATOMIC_OR__GFX09                        0x00000049
#define SQ_FLAT_ATOMIC_OR_X2__GFX09                     0x00000069
#define SQ_FLAT_ATOMIC_SMAX__GFX09                      0x00000046
#define SQ_FLAT_ATOMIC_SMAX_X2__GFX09                   0x00000066
#define SQ_FLAT_ATOMIC_SMIN__GFX09                      0x00000044
#define SQ_FLAT_ATOMIC_SMIN_X2__GFX09                   0x00000064
#define SQ_FLAT_ATOMIC_SUB__GFX09                       0x00000043
#define SQ_FLAT_ATOMIC_SUB_X2__GFX09                    0x00000063
#define SQ_FLAT_ATOMIC_SWAP__GFX09                      0x00000040
#define SQ_FLAT_ATOMIC_SWAP_X2__GFX09                   0x00000060
#define SQ_FLAT_ATOMIC_UMAX__GFX09                      0x00000047
#define SQ_FLAT_ATOMIC_UMAX_X2__GFX09                   0x00000067
#define SQ_FLAT_ATOMIC_UMIN__GFX09                      0x00000045
#define SQ_FLAT_ATOMIC_UMIN_X2__GFX09                   0x00000065
#define SQ_FLAT_ATOMIC_XOR__GFX09                       0x0000004a
#define SQ_FLAT_ATOMIC_XOR_X2__GFX09                    0x0000006a
#define SQ_FLAT_LOAD_DWORD__GFX09                       0x00000014
#define SQ_FLAT_LOAD_DWORDX2__GFX09                     0x00000015
#define SQ_FLAT_LOAD_DWORDX3__GFX09                     0x00000016
#define SQ_FLAT_LOAD_DWORDX4__GFX09                     0x00000017
#define SQ_FLAT_LOAD_SBYTE__GFX09                       0x00000011
#define SQ_FLAT_LOAD_SSHORT__GFX09                      0x00000013
#define SQ_FLAT_LOAD_UBYTE__GFX09                       0x00000010
#define SQ_FLAT_LOAD_USHORT__GFX09                      0x00000012
#define SQ_FLAT_SCRATCH_HI__GFX09                       0x00000067
#define SQ_FLAT_SCRATCH_LO__GFX09                       0x00000066
#define SQ_FLAT_STORE_BYTE__GFX09                       0x00000018
#define SQ_FLAT_STORE_DWORD__GFX09                      0x0000001c
#define SQ_FLAT_STORE_DWORDX2__GFX09                    0x0000001d
#define SQ_FLAT_STORE_DWORDX3__GFX09                    0x0000001e
#define SQ_FLAT_STORE_DWORDX4__GFX09                    0x0000001f
#define SQ_FLAT_STORE_SHORT__GFX09                      0x0000001a
#define SQ_GE__GFX09                                    0x00000006
#define SQ_GFXDEC_BEGIN                                 0x0000a000
#define SQ_GFXDEC_END                                   0x0000c000
#define SQ_GFXDEC_STATE_ID_SHIFT                        0x0000000a
#define SQ_GS_OP_CUT__GFX09                             0x00000001
#define SQ_GS_OP_EMIT__GFX09                            0x00000002
#define SQ_GS_OP_EMIT_CUT__GFX09                        0x00000003
#define SQ_GS_OP_NOP__GFX09                             0x00000000
#define SQ_GT__GFX09                                    0x00000004
#define SQ_HWREG_ID_SHIFT__GFX09                        0x00000000
#define SQ_HWREG_ID_SIZE__GFX09                         0x00000006
#define SQ_HWREG_OFFSET_SHIFT__GFX09                    0x00000006
#define SQ_HWREG_OFFSET_SIZE__GFX09                     0x00000005
#define SQ_HWREG_SIZE_SHIFT__GFX09                      0x0000000b
#define SQ_HWREG_SIZE_SIZE__GFX09                       0x00000005
#define SQ_HW_REG_GPR_ALLOC__GFX09                      0x00000005
#define SQ_HW_REG_HW_ID__GFX09                          0x00000004
#define SQ_HW_REG_IB_DBG0__GFX09                        0x0000000c
#define SQ_HW_REG_IB_DBG1__GFX09                        0x0000000d
#define SQ_HW_REG_IB_STS__GFX09                         0x00000007
#define SQ_HW_REG_INST_DW0__GFX09                       0x0000000a
#define SQ_HW_REG_INST_DW1__GFX09                       0x0000000b
#define SQ_HW_REG_LDS_ALLOC__GFX09                      0x00000006
#define SQ_HW_REG_MODE__GFX09                           0x00000001
#define SQ_HW_REG_PC_HI__GFX09                          0x00000009
#define SQ_HW_REG_PC_LO__GFX09                          0x00000008
#define SQ_HW_REG_STATUS__GFX09                         0x00000002
#define SQ_HW_REG_TRAPSTS__GFX09                        0x00000003
#define SQ_IMAGE_ATOMIC_ADD__GFX09                      0x00000012
#define SQ_IMAGE_ATOMIC_AND__GFX09                      0x00000018
#define SQ_IMAGE_ATOMIC_CMPSWAP__GFX09                  0x00000011
#define SQ_IMAGE_ATOMIC_DEC__GFX09                      0x0000001c
#define SQ_IMAGE_ATOMIC_INC__GFX09                      0x0000001b
#define SQ_IMAGE_ATOMIC_OR__GFX09                       0x00000019
#define SQ_IMAGE_ATOMIC_SMAX__GFX09                     0x00000016
#define SQ_IMAGE_ATOMIC_SMIN__GFX09                     0x00000014
#define SQ_IMAGE_ATOMIC_SUB__GFX09                      0x00000013
#define SQ_IMAGE_ATOMIC_SWAP__GFX09                     0x00000010
#define SQ_IMAGE_ATOMIC_UMAX__GFX09                     0x00000017
#define SQ_IMAGE_ATOMIC_UMIN__GFX09                     0x00000015
#define SQ_IMAGE_ATOMIC_XOR__GFX09                      0x0000001a
#define SQ_IMAGE_GATHER4__GFX09                         0x00000040
#define SQ_IMAGE_GATHER4_B__GFX09                       0x00000045
#define SQ_IMAGE_GATHER4_B_CL__GFX09                    0x00000046
#define SQ_IMAGE_GATHER4_B_CL_O__GFX09                  0x00000056
#define SQ_IMAGE_GATHER4_B_O__GFX09                     0x00000055
#define SQ_IMAGE_GATHER4_C__GFX09                       0x00000048
#define SQ_IMAGE_GATHER4_CL__GFX09                      0x00000041
#define SQ_IMAGE_GATHER4_CL_O__GFX09                    0x00000051
#define SQ_IMAGE_GATHER4_C_B__GFX09                     0x0000004d
#define SQ_IMAGE_GATHER4_C_B_CL__GFX09                  0x0000004e
#define SQ_IMAGE_GATHER4_C_B_CL_O__GFX09                0x0000005e
#define SQ_IMAGE_GATHER4_C_B_O__GFX09                   0x0000005d
#define SQ_IMAGE_GATHER4_C_CL__GFX09                    0x00000049
#define SQ_IMAGE_GATHER4_C_CL_O__GFX09                  0x00000059
#define SQ_IMAGE_GATHER4_C_L__GFX09                     0x0000004c
#define SQ_IMAGE_GATHER4_C_LZ__GFX09                    0x0000004f
#define SQ_IMAGE_GATHER4_C_LZ_O__GFX09                  0x0000005f
#define SQ_IMAGE_GATHER4_C_L_O__GFX09                   0x0000005c
#define SQ_IMAGE_GATHER4_C_O__GFX09                     0x00000058
#define SQ_IMAGE_GATHER4_L__GFX09                       0x00000044
#define SQ_IMAGE_GATHER4_LZ__GFX09                      0x00000047
#define SQ_IMAGE_GATHER4_LZ_O__GFX09                    0x00000057
#define SQ_IMAGE_GATHER4_L_O__GFX09                     0x00000054
#define SQ_IMAGE_GATHER4_O__GFX09                       0x00000050
#define SQ_IMAGE_GET_LOD__GFX09                         0x00000060
#define SQ_IMAGE_GET_RESINFO__GFX09                     0x0000000e
#define SQ_IMAGE_LOAD__GFX09                            0x00000000
#define SQ_IMAGE_LOAD_MIP__GFX09                        0x00000001
#define SQ_IMAGE_LOAD_MIP_PCK__GFX09                    0x00000004
#define SQ_IMAGE_LOAD_MIP_PCK_SGN__GFX09                0x00000005
#define SQ_IMAGE_LOAD_PCK__GFX09                        0x00000002
#define SQ_IMAGE_LOAD_PCK_SGN__GFX09                    0x00000003
#define SQ_IMAGE_RSRC256__GFX09                         0x0000007e
#define SQ_IMAGE_SAMPLE__GFX09                          0x00000020
#define SQ_IMAGE_SAMPLER__GFX09                         0x0000007f
#define SQ_IMAGE_SAMPLE_B__GFX09                        0x00000025
#define SQ_IMAGE_SAMPLE_B_CL__GFX09                     0x00000026
#define SQ_IMAGE_SAMPLE_B_CL_O__GFX09                   0x00000036
#define SQ_IMAGE_SAMPLE_B_O__GFX09                      0x00000035
#define SQ_IMAGE_SAMPLE_C__GFX09                        0x00000028
#define SQ_IMAGE_SAMPLE_CD__GFX09                       0x00000068
#define SQ_IMAGE_SAMPLE_CD_CL__GFX09                    0x00000069
#define SQ_IMAGE_SAMPLE_CD_CL_O__GFX09                  0x0000006d
#define SQ_IMAGE_SAMPLE_CD_O__GFX09                     0x0000006c
#define SQ_IMAGE_SAMPLE_CL__GFX09                       0x00000021
#define SQ_IMAGE_SAMPLE_CL_O__GFX09                     0x00000031
#define SQ_IMAGE_SAMPLE_C_B__GFX09                      0x0000002d
#define SQ_IMAGE_SAMPLE_C_B_CL__GFX09                   0x0000002e
#define SQ_IMAGE_SAMPLE_C_B_CL_O__GFX09                 0x0000003e
#define SQ_IMAGE_SAMPLE_C_B_O__GFX09                    0x0000003d
#define SQ_IMAGE_SAMPLE_C_CD__GFX09                     0x0000006a
#define SQ_IMAGE_SAMPLE_C_CD_CL__GFX09                  0x0000006b
#define SQ_IMAGE_SAMPLE_C_CD_CL_O__GFX09                0x0000006f
#define SQ_IMAGE_SAMPLE_C_CD_O__GFX09                   0x0000006e
#define SQ_IMAGE_SAMPLE_C_CL__GFX09                     0x00000029
#define SQ_IMAGE_SAMPLE_C_CL_O__GFX09                   0x00000039
#define SQ_IMAGE_SAMPLE_C_D__GFX09                      0x0000002a
#define SQ_IMAGE_SAMPLE_C_D_CL__GFX09                   0x0000002b
#define SQ_IMAGE_SAMPLE_C_D_CL_O__GFX09                 0x0000003b
#define SQ_IMAGE_SAMPLE_C_D_O__GFX09                    0x0000003a
#define SQ_IMAGE_SAMPLE_C_L__GFX09                      0x0000002c
#define SQ_IMAGE_SAMPLE_C_LZ__GFX09                     0x0000002f
#define SQ_IMAGE_SAMPLE_C_LZ_O__GFX09                   0x0000003f
#define SQ_IMAGE_SAMPLE_C_L_O__GFX09                    0x0000003c
#define SQ_IMAGE_SAMPLE_C_O__GFX09                      0x00000038
#define SQ_IMAGE_SAMPLE_D__GFX09                        0x00000022
#define SQ_IMAGE_SAMPLE_D_CL__GFX09                     0x00000023
#define SQ_IMAGE_SAMPLE_D_CL_O__GFX09                   0x00000033
#define SQ_IMAGE_SAMPLE_D_O__GFX09                      0x00000032
#define SQ_IMAGE_SAMPLE_L__GFX09                        0x00000024
#define SQ_IMAGE_SAMPLE_LZ__GFX09                       0x00000027
#define SQ_IMAGE_SAMPLE_LZ_O__GFX09                     0x00000037
#define SQ_IMAGE_SAMPLE_L_O__GFX09                      0x00000034
#define SQ_IMAGE_SAMPLE_O__GFX09                        0x00000030
#define SQ_IMAGE_STORE__GFX09                           0x00000008
#define SQ_IMAGE_STORE_MIP__GFX09                       0x00000009
#define SQ_IMAGE_STORE_MIP_PCK__GFX09                   0x0000000b
#define SQ_IMAGE_STORE_PCK__GFX09                       0x0000000a
#define SQ_L1__GFX09                                    0x00000001
#define SQ_L10__GFX09                                   0x0000000a
#define SQ_L11__GFX09                                   0x0000000b
#define SQ_L12__GFX09                                   0x0000000c
#define SQ_L13__GFX09                                   0x0000000d
#define SQ_L14__GFX09                                   0x0000000e
#define SQ_L15__GFX09                                   0x0000000f
#define SQ_L2__GFX09                                    0x00000002
#define SQ_L3__GFX09                                    0x00000003
#define SQ_L4__GFX09                                    0x00000004
#define SQ_L5__GFX09                                    0x00000005
#define SQ_L6__GFX09                                    0x00000006
#define SQ_L7__GFX09                                    0x00000007
#define SQ_L8__GFX09                                    0x00000008
#define SQ_L9__GFX09                                    0x00000009
#define SQ_LE__GFX09                                    0x00000003
#define SQ_LG__GFX09                                    0x00000005
#define SQ_LT__GFX09                                    0x00000001
#define SQ_M0__GFX09                                    0x0000007c
#define SQ_MAX_PGM_SGPRS                                0x00000068
#define SQ_MAX_PGM_VGPRS                                0x00000100
#define SQ_MSG_GS__GFX09                                0x00000002
#define SQ_MSG_GS_DONE__GFX09                           0x00000003
#define SQ_MSG_INTERRUPT__GFX09                         0x00000001
#define SQ_MSG_SAVEWAVE__GFX09                          0x00000004
#define SQ_MSG_SYSMSG__GFX09                            0x0000000f
#define SQ_NE__GFX09                                    0x00000005
#define SQ_NEQ__GFX09                                   0x0000000d
#define SQ_NGE__GFX09                                   0x00000009
#define SQ_NGT__GFX09                                   0x0000000b
#define SQ_NLE__GFX09                                   0x0000000c
#define SQ_NLG__GFX09                                   0x0000000a
#define SQ_NLT__GFX09                                   0x0000000e
#define SQ_NUM_ATTR__GFX09                              0x00000021
#define SQ_NUM_SGPR__GFX09                              0x00000066
#define SQ_NUM_TTMP__GFX09                              0x00000010
#define SQ_NUM_VGPR__GFX09                              0x00000100
#define SQ_O__GFX09                                     0x00000007
#define SQ_OMOD_D2__GFX09                               0x00000003
#define SQ_OMOD_M2__GFX09                               0x00000001
#define SQ_OMOD_M4__GFX09                               0x00000002
#define SQ_OMOD_OFF__GFX09                              0x00000000
#define SQ_PARAM_P0__GFX09                              0x00000002
#define SQ_PARAM_P10__GFX09                             0x00000000
#define SQ_PARAM_P20__GFX09                             0x00000001
#define SQ_R1__GFX09                                    0x00000001
#define SQ_R10__GFX09                                   0x0000000a
#define SQ_R11__GFX09                                   0x0000000b
#define SQ_R12__GFX09                                   0x0000000c
#define SQ_R13__GFX09                                   0x0000000d
#define SQ_R14__GFX09                                   0x0000000e
#define SQ_R15__GFX09                                   0x0000000f
#define SQ_R2__GFX09                                    0x00000002
#define SQ_R3__GFX09                                    0x00000003
#define SQ_R4__GFX09                                    0x00000004
#define SQ_R5__GFX09                                    0x00000005
#define SQ_R6__GFX09                                    0x00000006
#define SQ_R7__GFX09                                    0x00000007
#define SQ_R8__GFX09                                    0x00000008
#define SQ_R9__GFX09                                    0x00000009
#define SQ_SDWA_BYTE_0__GFX09                           0x00000000
#define SQ_SDWA_BYTE_1__GFX09                           0x00000001
#define SQ_SDWA_BYTE_2__GFX09                           0x00000002
#define SQ_SDWA_BYTE_3__GFX09                           0x00000003
#define SQ_SDWA_DWORD__GFX09                            0x00000006
#define SQ_SDWA_UNUSED_PAD__GFX09                       0x00000000
#define SQ_SDWA_UNUSED_PRESERVE__GFX09                  0x00000002
#define SQ_SDWA_UNUSED_SEXT__GFX09                      0x00000001
#define SQ_SDWA_WORD_0__GFX09                           0x00000004
#define SQ_SDWA_WORD_1__GFX09                           0x00000005
#define SQ_SENDMSG_GSOP_SHIFT__GFX09                    0x00000004
#define SQ_SENDMSG_GSOP_SIZE__GFX09                     0x00000002
#define SQ_SENDMSG_MSG_SHIFT__GFX09                     0x00000000
#define SQ_SENDMSG_MSG_SIZE__GFX09                      0x00000004
#define SQ_SENDMSG_STREAMID_SHIFT__GFX09                0x00000008
#define SQ_SENDMSG_STREAMID_SIZE__GFX09                 0x00000002
#define SQ_SENDMSG_SYSTEM_SHIFT__GFX09                  0x00000004
#define SQ_SENDMSG_SYSTEM_SIZE__GFX09                   0x00000003
#define SQ_SGPR0__GFX09                                 0x00000000
#define SQ_SRC_0__GFX09                                 0x00000080
#define SQ_SRC_0_5__GFX09                               0x000000f0
#define SQ_SRC_1__GFX09                                 0x000000f2
#define SQ_SRC_10_INT__GFX09                            0x0000008a
#define SQ_SRC_11_INT__GFX09                            0x0000008b
#define SQ_SRC_12_INT__GFX09                            0x0000008c
#define SQ_SRC_13_INT__GFX09                            0x0000008d
#define SQ_SRC_14_INT__GFX09                            0x0000008e
#define SQ_SRC_15_INT__GFX09                            0x0000008f
#define SQ_SRC_16_INT__GFX09                            0x00000090
#define SQ_SRC_17_INT__GFX09                            0x00000091
#define SQ_SRC_18_INT__GFX09                            0x00000092
#define SQ_SRC_19_INT__GFX09                            0x00000093
#define SQ_SRC_1_INT__GFX09                             0x00000081
#define SQ_SRC_2__GFX09                                 0x000000f4
#define SQ_SRC_20_INT__GFX09                            0x00000094
#define SQ_SRC_21_INT__GFX09                            0x00000095
#define SQ_SRC_22_INT__GFX09                            0x00000096
#define SQ_SRC_23_INT__GFX09                            0x00000097
#define SQ_SRC_24_INT__GFX09                            0x00000098
#define SQ_SRC_25_INT__GFX09                            0x00000099
#define SQ_SRC_26_INT__GFX09                            0x0000009a
#define SQ_SRC_27_INT__GFX09                            0x0000009b
#define SQ_SRC_28_INT__GFX09                            0x0000009c
#define SQ_SRC_29_INT__GFX09                            0x0000009d
#define SQ_SRC_2_INT__GFX09                             0x00000082
#define SQ_SRC_30_INT__GFX09                            0x0000009e
#define SQ_SRC_31_INT__GFX09                            0x0000009f
#define SQ_SRC_32_INT__GFX09                            0x000000a0
#define SQ_SRC_33_INT__GFX09                            0x000000a1
#define SQ_SRC_34_INT__GFX09                            0x000000a2
#define SQ_SRC_35_INT__GFX09                            0x000000a3
#define SQ_SRC_36_INT__GFX09                            0x000000a4
#define SQ_SRC_37_INT__GFX09                            0x000000a5
#define SQ_SRC_38_INT__GFX09                            0x000000a6
#define SQ_SRC_39_INT__GFX09                            0x000000a7
#define SQ_SRC_3_INT__GFX09                             0x00000083
#define SQ_SRC_4__GFX09                                 0x000000f6
#define SQ_SRC_40_INT__GFX09                            0x000000a8
#define SQ_SRC_41_INT__GFX09                            0x000000a9
#define SQ_SRC_42_INT__GFX09                            0x000000aa
#define SQ_SRC_43_INT__GFX09                            0x000000ab
#define SQ_SRC_44_INT__GFX09                            0x000000ac
#define SQ_SRC_45_INT__GFX09                            0x000000ad
#define SQ_SRC_46_INT__GFX09                            0x000000ae
#define SQ_SRC_47_INT__GFX09                            0x000000af
#define SQ_SRC_48_INT__GFX09                            0x000000b0
#define SQ_SRC_49_INT__GFX09                            0x000000b1
#define SQ_SRC_4_INT__GFX09                             0x00000084
#define SQ_SRC_50_INT__GFX09                            0x000000b2
#define SQ_SRC_51_INT__GFX09                            0x000000b3
#define SQ_SRC_52_INT__GFX09                            0x000000b4
#define SQ_SRC_53_INT__GFX09                            0x000000b5
#define SQ_SRC_54_INT__GFX09                            0x000000b6
#define SQ_SRC_55_INT__GFX09                            0x000000b7
#define SQ_SRC_56_INT__GFX09                            0x000000b8
#define SQ_SRC_57_INT__GFX09                            0x000000b9
#define SQ_SRC_58_INT__GFX09                            0x000000ba
#define SQ_SRC_59_INT__GFX09                            0x000000bb
#define SQ_SRC_5_INT__GFX09                             0x00000085
#define SQ_SRC_60_INT__GFX09                            0x000000bc
#define SQ_SRC_61_INT__GFX09                            0x000000bd
#define SQ_SRC_62_INT__GFX09                            0x000000be
#define SQ_SRC_63_INT__GFX09                            0x000000bf
#define SQ_SRC_64_INT__GFX09                            0x000000c0
#define SQ_SRC_6_INT__GFX09                             0x00000086
#define SQ_SRC_7_INT__GFX09                             0x00000087
#define SQ_SRC_8_INT__GFX09                             0x00000088
#define SQ_SRC_9_INT__GFX09                             0x00000089
#define SQ_SRC_DPP__GFX09                               0x000000fa
#define SQ_SRC_EXECZ__GFX09                             0x000000fc
#define SQ_SRC_INV_2PI__GFX09                           0x000000f8
#define SQ_SRC_LDS_DIRECT__GFX09                        0x000000fe
#define SQ_SRC_LITERAL__GFX09                           0x000000ff
#define SQ_SRC_M_0_5__GFX09                             0x000000f1
#define SQ_SRC_M_1__GFX09                               0x000000f3
#define SQ_SRC_M_10_INT__GFX09                          0x000000ca
#define SQ_SRC_M_11_INT__GFX09                          0x000000cb
#define SQ_SRC_M_12_INT__GFX09                          0x000000cc
#define SQ_SRC_M_13_INT__GFX09                          0x000000cd
#define SQ_SRC_M_14_INT__GFX09                          0x000000ce
#define SQ_SRC_M_15_INT__GFX09                          0x000000cf
#define SQ_SRC_M_16_INT__GFX09                          0x000000d0
#define SQ_SRC_M_1_INT__GFX09                           0x000000c1
#define SQ_SRC_M_2__GFX09                               0x000000f5
#define SQ_SRC_M_2_INT__GFX09                           0x000000c2
#define SQ_SRC_M_3_INT__GFX09                           0x000000c3
#define SQ_SRC_M_4__GFX09                               0x000000f7
#define SQ_SRC_M_4_INT__GFX09                           0x000000c4
#define SQ_SRC_M_5_INT__GFX09                           0x000000c5
#define SQ_SRC_M_6_INT__GFX09                           0x000000c6
#define SQ_SRC_M_7_INT__GFX09                           0x000000c7
#define SQ_SRC_M_8_INT__GFX09                           0x000000c8
#define SQ_SRC_M_9_INT__GFX09                           0x000000c9
#define SQ_SRC_SCC__GFX09                               0x000000fd
#define SQ_SRC_SDWA__GFX09                              0x000000f9
#define SQ_SRC_VCCZ__GFX09                              0x000000fb
#define SQ_SRC_VGPR0__GFX09                             0x00000100
#define SQ_SRC_VGPR_BIT__GFX09                          0x00000100
#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT__GFX09           0x00000001
#define SQ_SYSMSG_OP_HOST_TRAP_ACK__GFX09               0x00000003
#define SQ_SYSMSG_OP_REG_RD__GFX09                      0x00000002
#define SQ_SYSMSG_OP_TTRACE_PC__GFX09                   0x00000004
#define SQ_S_ABSDIFF_I32__GFX09                         0x0000002a
#define SQ_S_ABS_I32__GFX09                             0x00000030
#define SQ_S_ADDC_U32__GFX09                            0x00000004
#define SQ_S_ADDK_I32__GFX09                            0x0000000e
#define SQ_S_ADD_I32__GFX09                             0x00000002
#define SQ_S_ADD_U32__GFX09                             0x00000000
#define SQ_S_ANDN2_B32__GFX09                           0x00000012
#define SQ_S_ANDN2_B64__GFX09                           0x00000013
#define SQ_S_ANDN2_SAVEEXEC_B64__GFX09                  0x00000023
#define SQ_S_AND_B32__GFX09                             0x0000000c
#define SQ_S_AND_B64__GFX09                             0x0000000d
#define SQ_S_AND_SAVEEXEC_B64__GFX09                    0x00000020
#define SQ_S_ASHR_I32__GFX09                            0x00000020
#define SQ_S_ASHR_I64__GFX09                            0x00000021
#define SQ_S_ATC_PROBE__GFX09                           0x00000026
#define SQ_S_ATC_PROBE_BUFFER__GFX09                    0x00000027
#define SQ_S_BARRIER__GFX09                             0x0000000a
#define SQ_S_BCNT0_I32_B32__GFX09                       0x0000000a
#define SQ_S_BCNT0_I32_B64__GFX09                       0x0000000b
#define SQ_S_BCNT1_I32_B32__GFX09                       0x0000000c
#define SQ_S_BCNT1_I32_B64__GFX09                       0x0000000d
#define SQ_S_BFE_I32__GFX09                             0x00000026
#define SQ_S_BFE_I64__GFX09                             0x00000028
#define SQ_S_BFE_U32__GFX09                             0x00000025
#define SQ_S_BFE_U64__GFX09                             0x00000027
#define SQ_S_BFM_B32__GFX09                             0x00000022
#define SQ_S_BFM_B64__GFX09                             0x00000023
#define SQ_S_BITCMP0_B32__GFX09                         0x0000000c
#define SQ_S_BITCMP0_B64__GFX09                         0x0000000e
#define SQ_S_BITCMP1_B32__GFX09                         0x0000000d
#define SQ_S_BITCMP1_B64__GFX09                         0x0000000f
#define SQ_S_BITSET0_B32__GFX09                         0x00000018
#define SQ_S_BITSET0_B64__GFX09                         0x00000019
#define SQ_S_BITSET1_B32__GFX09                         0x0000001a
#define SQ_S_BITSET1_B64__GFX09                         0x0000001b
#define SQ_S_BRANCH__GFX09                              0x00000002
#define SQ_S_BREV_B32__GFX09                            0x00000008
#define SQ_S_BREV_B64__GFX09                            0x00000009
#define SQ_S_BUFFER_ATOMIC_ADD__GFX09                   0x00000042
#define SQ_S_BUFFER_ATOMIC_ADD_X2__GFX09                0x00000062
#define SQ_S_BUFFER_ATOMIC_AND__GFX09                   0x00000048
#define SQ_S_BUFFER_ATOMIC_AND_X2__GFX09                0x00000068
#define SQ_S_BUFFER_ATOMIC_CMPSWAP__GFX09               0x00000041
#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2__GFX09            0x00000061
#define SQ_S_BUFFER_ATOMIC_DEC__GFX09                   0x0000004c
#define SQ_S_BUFFER_ATOMIC_DEC_X2__GFX09                0x0000006c
#define SQ_S_BUFFER_ATOMIC_INC__GFX09                   0x0000004b
#define SQ_S_BUFFER_ATOMIC_INC_X2__GFX09                0x0000006b
#define SQ_S_BUFFER_ATOMIC_OR__GFX09                    0x00000049
#define SQ_S_BUFFER_ATOMIC_OR_X2__GFX09                 0x00000069
#define SQ_S_BUFFER_ATOMIC_SMAX__GFX09                  0x00000046
#define SQ_S_BUFFER_ATOMIC_SMAX_X2__GFX09               0x00000066
#define SQ_S_BUFFER_ATOMIC_SMIN__GFX09                  0x00000044
#define SQ_S_BUFFER_ATOMIC_SMIN_X2__GFX09               0x00000064
#define SQ_S_BUFFER_ATOMIC_SUB__GFX09                   0x00000043
#define SQ_S_BUFFER_ATOMIC_SUB_X2__GFX09                0x00000063
#define SQ_S_BUFFER_ATOMIC_SWAP__GFX09                  0x00000040
#define SQ_S_BUFFER_ATOMIC_SWAP_X2__GFX09               0x00000060
#define SQ_S_BUFFER_ATOMIC_UMAX__GFX09                  0x00000047
#define SQ_S_BUFFER_ATOMIC_UMAX_X2__GFX09               0x00000067
#define SQ_S_BUFFER_ATOMIC_UMIN__GFX09                  0x00000045
#define SQ_S_BUFFER_ATOMIC_UMIN_X2__GFX09               0x00000065
#define SQ_S_BUFFER_ATOMIC_XOR__GFX09                   0x0000004a
#define SQ_S_BUFFER_ATOMIC_XOR_X2__GFX09                0x0000006a
#define SQ_S_BUFFER_LOAD_DWORD__GFX09                   0x00000008
#define SQ_S_BUFFER_LOAD_DWORDX16__GFX09                0x0000000c
#define SQ_S_BUFFER_LOAD_DWORDX2__GFX09                 0x00000009
#define SQ_S_BUFFER_LOAD_DWORDX4__GFX09                 0x0000000a
#define SQ_S_BUFFER_LOAD_DWORDX8__GFX09                 0x0000000b
#define SQ_S_BUFFER_STORE_DWORD__GFX09                  0x00000018
#define SQ_S_BUFFER_STORE_DWORDX2__GFX09                0x00000019
#define SQ_S_BUFFER_STORE_DWORDX4__GFX09                0x0000001a
#define SQ_S_CBRANCH_CDBGSYS__GFX09                     0x00000017
#define SQ_S_CBRANCH_CDBGSYS_AND_USER__GFX09            0x0000001a
#define SQ_S_CBRANCH_CDBGSYS_OR_USER__GFX09             0x00000019
#define SQ_S_CBRANCH_CDBGUSER__GFX09                    0x00000018
#define SQ_S_CBRANCH_EXECNZ__GFX09                      0x00000009
#define SQ_S_CBRANCH_EXECZ__GFX09                       0x00000008
#define SQ_S_CBRANCH_G_FORK__GFX09                      0x00000029
#define SQ_S_CBRANCH_I_FORK__GFX09                      0x00000010
#define SQ_S_CBRANCH_JOIN__GFX09                        0x0000002e
#define SQ_S_CBRANCH_SCC0__GFX09                        0x00000004
#define SQ_S_CBRANCH_SCC1__GFX09                        0x00000005
#define SQ_S_CBRANCH_VCCNZ__GFX09                       0x00000007
#define SQ_S_CBRANCH_VCCZ__GFX09                        0x00000006
#define SQ_S_CMOVK_I32__GFX09                           0x00000001
#define SQ_S_CMOV_B32__GFX09                            0x00000002
#define SQ_S_CMOV_B64__GFX09                            0x00000003
#define SQ_S_CMPK_EQ_I32__GFX09                         0x00000002
#define SQ_S_CMPK_EQ_U32__GFX09                         0x00000008
#define SQ_S_CMPK_GE_I32__GFX09                         0x00000005
#define SQ_S_CMPK_GE_U32__GFX09                         0x0000000b
#define SQ_S_CMPK_GT_I32__GFX09                         0x00000004
#define SQ_S_CMPK_GT_U32__GFX09                         0x0000000a
#define SQ_S_CMPK_LE_I32__GFX09                         0x00000007
#define SQ_S_CMPK_LE_U32__GFX09                         0x0000000d
#define SQ_S_CMPK_LG_I32__GFX09                         0x00000003
#define SQ_S_CMPK_LG_U32__GFX09                         0x00000009
#define SQ_S_CMPK_LT_I32__GFX09                         0x00000006
#define SQ_S_CMPK_LT_U32__GFX09                         0x0000000c
#define SQ_S_CMP_EQ_I32__GFX09                          0x00000000
#define SQ_S_CMP_EQ_U32__GFX09                          0x00000006
#define SQ_S_CMP_EQ_U64__GFX09                          0x00000012
#define SQ_S_CMP_GE_I32__GFX09                          0x00000003
#define SQ_S_CMP_GE_U32__GFX09                          0x00000009
#define SQ_S_CMP_GT_I32__GFX09                          0x00000002
#define SQ_S_CMP_GT_U32__GFX09                          0x00000008
#define SQ_S_CMP_LE_I32__GFX09                          0x00000005
#define SQ_S_CMP_LE_U32__GFX09                          0x0000000b
#define SQ_S_CMP_LG_I32__GFX09                          0x00000001
#define SQ_S_CMP_LG_U32__GFX09                          0x00000007
#define SQ_S_CMP_LG_U64__GFX09                          0x00000013
#define SQ_S_CMP_LT_I32__GFX09                          0x00000004
#define SQ_S_CMP_LT_U32__GFX09                          0x0000000a
#define SQ_S_CSELECT_B32__GFX09                         0x0000000a
#define SQ_S_CSELECT_B64__GFX09                         0x0000000b
#define SQ_S_DCACHE_INV__GFX09                          0x00000020
#define SQ_S_DCACHE_INV_VOL__GFX09                      0x00000022
#define SQ_S_DCACHE_WB__GFX09                           0x00000021
#define SQ_S_DCACHE_WB_VOL__GFX09                       0x00000023
#define SQ_S_DECPERFLEVEL__GFX09                        0x00000015
#define SQ_S_ENDPGM__GFX09                              0x00000001
#define SQ_S_ENDPGM_SAVED__GFX09                        0x0000001b
#define SQ_S_FF0_I32_B32__GFX09                         0x0000000e
#define SQ_S_FF0_I32_B64__GFX09                         0x0000000f
#define SQ_S_FF1_I32_B32__GFX09                         0x00000010
#define SQ_S_FF1_I32_B64__GFX09                         0x00000011
#define SQ_S_FLBIT_I32__GFX09                           0x00000014
#define SQ_S_FLBIT_I32_B32__GFX09                       0x00000012
#define SQ_S_FLBIT_I32_B64__GFX09                       0x00000013
#define SQ_S_FLBIT_I32_I64__GFX09                       0x00000015
#define SQ_S_GETPC_B64__GFX09                           0x0000001c
#define SQ_S_GETREG_B32__GFX09                          0x00000011
#define SQ_S_GETREG_REGRD_B32__GFX09                    0x00000013
#define SQ_S_ICACHE_INV__GFX09                          0x00000013
#define SQ_S_INCPERFLEVEL__GFX09                        0x00000014
#define SQ_S_LOAD_DWORD__GFX09                          0x00000000
#define SQ_S_LOAD_DWORDX16__GFX09                       0x00000004
#define SQ_S_LOAD_DWORDX2__GFX09                        0x00000001
#define SQ_S_LOAD_DWORDX4__GFX09                        0x00000002
#define SQ_S_LOAD_DWORDX8__GFX09                        0x00000003
#define SQ_S_LSHL_B32__GFX09                            0x0000001c
#define SQ_S_LSHL_B64__GFX09                            0x0000001d
#define SQ_S_LSHR_B32__GFX09                            0x0000001e
#define SQ_S_LSHR_B64__GFX09                            0x0000001f
#define SQ_S_MAX_I32__GFX09                             0x00000008
#define SQ_S_MAX_U32__GFX09                             0x00000009
#define SQ_S_MEMREALTIME__GFX09                         0x00000025
#define SQ_S_MEMTIME__GFX09                             0x00000024
#define SQ_S_MIN_I32__GFX09                             0x00000006
#define SQ_S_MIN_U32__GFX09                             0x00000007
#define SQ_S_MOVK_I32__GFX09                            0x00000000
#define SQ_S_MOVRELD_B32__GFX09                         0x0000002c
#define SQ_S_MOVRELD_B64__GFX09                         0x0000002d
#define SQ_S_MOVRELS_B32__GFX09                         0x0000002a
#define SQ_S_MOVRELS_B64__GFX09                         0x0000002b
#define SQ_S_MOV_B32__GFX09                             0x00000000
#define SQ_S_MOV_B64__GFX09                             0x00000001
#define SQ_S_MOV_FED_B32__GFX09                         0x00000031
#define SQ_S_MOV_REGRD_B32__GFX09                       0x0000002f
#define SQ_S_MULK_I32__GFX09                            0x0000000f
#define SQ_S_MUL_I32__GFX09                             0x00000024
#define SQ_S_NAND_B32__GFX09                            0x00000016
#define SQ_S_NAND_B64__GFX09                            0x00000017
#define SQ_S_NAND_SAVEEXEC_B64__GFX09                   0x00000025
#define SQ_S_NOP__GFX09                                 0x00000000
#define SQ_S_NOR_B32__GFX09                             0x00000018
#define SQ_S_NOR_B64__GFX09                             0x00000019
#define SQ_S_NOR_SAVEEXEC_B64__GFX09                    0x00000026
#define SQ_S_NOT_B32__GFX09                             0x00000004
#define SQ_S_NOT_B64__GFX09                             0x00000005
#define SQ_S_ORN2_B32__GFX09                            0x00000014
#define SQ_S_ORN2_B64__GFX09                            0x00000015
#define SQ_S_ORN2_SAVEEXEC_B64__GFX09                   0x00000024
#define SQ_S_OR_B32__GFX09                              0x0000000e
#define SQ_S_OR_B64__GFX09                              0x0000000f
#define SQ_S_OR_SAVEEXEC_B64__GFX09                     0x00000021
#define SQ_S_QUADMASK_B32__GFX09                        0x00000028
#define SQ_S_QUADMASK_B64__GFX09                        0x00000029
#define SQ_S_RFE_B64__GFX09                             0x0000001f
#define SQ_S_RFE_RESTORE_B64__GFX09                     0x0000002b
#define SQ_S_SENDMSG__GFX09                             0x00000010
#define SQ_S_SENDMSGHALT__GFX09                         0x00000011
#define SQ_S_SETHALT__GFX09                             0x0000000d
#define SQ_S_SETKILL__GFX09                             0x0000000b
#define SQ_S_SETPC_B64__GFX09                           0x0000001d
#define SQ_S_SETPRIO__GFX09                             0x0000000f
#define SQ_S_SETREG_B32__GFX09                          0x00000012
#define SQ_S_SETREG_IMM32_B32__GFX09                    0x00000014
#define SQ_S_SETVSKIP__GFX09                            0x00000010
#define SQ_S_SET_GPR_IDX_IDX__GFX09                     0x00000032
#define SQ_S_SET_GPR_IDX_MODE__GFX09                    0x0000001d
#define SQ_S_SET_GPR_IDX_OFF__GFX09                     0x0000001c
#define SQ_S_SET_GPR_IDX_ON__GFX09                      0x00000011
#define SQ_S_SEXT_I32_I16__GFX09                        0x00000017
#define SQ_S_SEXT_I32_I8__GFX09                         0x00000016
#define SQ_S_SLEEP__GFX09                               0x0000000e
#define SQ_S_STORE_DWORD__GFX09                         0x00000010
#define SQ_S_STORE_DWORDX2__GFX09                       0x00000011
#define SQ_S_STORE_DWORDX4__GFX09                       0x00000012
#define SQ_S_SUBB_U32__GFX09                            0x00000005
#define SQ_S_SUB_I32__GFX09                             0x00000003
#define SQ_S_SUB_U32__GFX09                             0x00000001
#define SQ_S_SWAPPC_B64__GFX09                          0x0000001e
#define SQ_S_TRAP__GFX09                                0x00000012
#define SQ_S_TTRACEDATA__GFX09                          0x00000016
#define SQ_S_WAITCNT__GFX09                             0x0000000c
#define SQ_S_WAKEUP__GFX09                              0x00000003
#define SQ_S_WQM_B32__GFX09                             0x00000006
#define SQ_S_WQM_B64__GFX09                             0x00000007
#define SQ_S_XNOR_B32__GFX09                            0x0000001a
#define SQ_S_XNOR_B64__GFX09                            0x0000001b
#define SQ_S_XNOR_SAVEEXEC_B64__GFX09                   0x00000027
#define SQ_S_XOR_B32__GFX09                             0x00000010
#define SQ_S_XOR_B64__GFX09                             0x00000011
#define SQ_S_XOR_SAVEEXEC_B64__GFX09                    0x00000022
#define SQ_T__GFX09                                     0x00000007
#define SQ_TBUFFER_LOAD_FORMAT_D16_X__GFX09             0x00000008
#define SQ_TBUFFER_LOAD_FORMAT_D16_XY__GFX09            0x00000009
#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ__GFX09           0x0000000a
#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW__GFX09          0x0000000b
#define SQ_TBUFFER_LOAD_FORMAT_X__GFX09                 0x00000000
#define SQ_TBUFFER_LOAD_FORMAT_XY__GFX09                0x00000001
#define SQ_TBUFFER_LOAD_FORMAT_XYZ__GFX09               0x00000002
#define SQ_TBUFFER_LOAD_FORMAT_XYZW__GFX09              0x00000003
#define SQ_TBUFFER_STORE_FORMAT_D16_X__GFX09            0x0000000c
#define SQ_TBUFFER_STORE_FORMAT_D16_XY__GFX09           0x0000000d
#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ__GFX09          0x0000000e
#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW__GFX09         0x0000000f
#define SQ_TBUFFER_STORE_FORMAT_X__GFX09                0x00000004
#define SQ_TBUFFER_STORE_FORMAT_XY__GFX09               0x00000005
#define SQ_TBUFFER_STORE_FORMAT_XYZ__GFX09              0x00000006
#define SQ_TBUFFER_STORE_FORMAT_XYZW__GFX09             0x00000007
#define SQ_THREAD_TRACE_TIME_UNIT__GFX09                0x00000004
#define SQ_TRU__GFX09                                   0x0000000f
#define SQ_TTMP0__GFX09                                 0x0000006c
#define SQ_TTMP1__GFX09                                 0x0000006d
#define SQ_TTMP10__GFX09                                0x00000076
#define SQ_TTMP11__GFX09                                0x00000077
#define SQ_TTMP2__GFX09                                 0x0000006e
#define SQ_TTMP3__GFX09                                 0x0000006f
#define SQ_TTMP4__GFX09                                 0x00000070
#define SQ_TTMP5__GFX09                                 0x00000071
#define SQ_TTMP6__GFX09                                 0x00000072
#define SQ_TTMP7__GFX09                                 0x00000073
#define SQ_TTMP8__GFX09                                 0x00000074
#define SQ_TTMP9__GFX09                                 0x00000075
#define SQ_U__GFX09                                     0x00000008
#define SQ_VCC_ALL__GFX09                               0x00000000
#define SQ_VCC_HI__GFX09                                0x0000006b
#define SQ_VCC_LO__GFX09                                0x0000006a
#define SQ_VGPR0__GFX09                                 0x00000000
#define SQ_V_ADD_F16__GFX09                             0x0000001f
#define SQ_V_ADD_F32__GFX09                             0x00000001
#define SQ_V_ADD_F64__GFX09                             0x00000280
#define SQ_V_ADD_I32__GFX09                             0x0000029c
#define SQ_V_ADD_U16__GFX09                             0x00000026
#define SQ_V_ADD_U32__GFX09                             0x00000034
#define SQ_V_ALIGNBIT_B32__GFX09                        0x000001ce
#define SQ_V_ALIGNBYTE_B32__GFX09                       0x000001cf
#define SQ_V_AND_B32__GFX09                             0x00000013
#define SQ_V_ASHRREV_I16__GFX09                         0x0000002c
#define SQ_V_ASHRREV_I32__GFX09                         0x00000011
#define SQ_V_ASHRREV_I64__GFX09                         0x00000291
#define SQ_V_BCNT_U32_B32__GFX09                        0x0000028b
#define SQ_V_BFE_I32__GFX09                             0x000001c9
#define SQ_V_BFE_U32__GFX09                             0x000001c8
#define SQ_V_BFI_B32__GFX09                             0x000001ca
#define SQ_V_BFM_B32__GFX09                             0x00000293
#define SQ_V_BFREV_B32__GFX09                           0x0000002c
#define SQ_V_CEIL_F16__GFX09                            0x00000045
#define SQ_V_CEIL_F32__GFX09                            0x0000001d
#define SQ_V_CEIL_F64__GFX09                            0x00000018
#define SQ_V_CLREXCP__GFX09                             0x00000035
#define SQ_V_CMPX_CLASS_F16__GFX09                      0x00000015
#define SQ_V_CMPX_CLASS_F32__GFX09                      0x00000011
#define SQ_V_CMPX_CLASS_F64__GFX09                      0x00000013
#define SQ_V_CMPX_EQ_F16__GFX09                         0x00000032
#define SQ_V_CMPX_EQ_F32__GFX09                         0x00000052
#define SQ_V_CMPX_EQ_F64__GFX09                         0x00000072
#define SQ_V_CMPX_EQ_I16__GFX09                         0x000000b2
#define SQ_V_CMPX_EQ_I32__GFX09                         0x000000d2
#define SQ_V_CMPX_EQ_I64__GFX09                         0x000000f2
#define SQ_V_CMPX_EQ_U16__GFX09                         0x000000ba
#define SQ_V_CMPX_EQ_U32__GFX09                         0x000000da
#define SQ_V_CMPX_EQ_U64__GFX09                         0x000000fa
#define SQ_V_CMPX_F_F16__GFX09                          0x00000030
#define SQ_V_CMPX_F_F32__GFX09                          0x00000050
#define SQ_V_CMPX_F_F64__GFX09                          0x00000070
#define SQ_V_CMPX_F_I16__GFX09                          0x000000b0
#define SQ_V_CMPX_F_I32__GFX09                          0x000000d0
#define SQ_V_CMPX_F_I64__GFX09                          0x000000f0
#define SQ_V_CMPX_F_U16__GFX09                          0x000000b8
#define SQ_V_CMPX_F_U32__GFX09                          0x000000d8
#define SQ_V_CMPX_F_U64__GFX09                          0x000000f8
#define SQ_V_CMPX_GE_F16__GFX09                         0x00000036
#define SQ_V_CMPX_GE_F32__GFX09                         0x00000056
#define SQ_V_CMPX_GE_F64__GFX09                         0x00000076
#define SQ_V_CMPX_GE_I16__GFX09                         0x000000b6
#define SQ_V_CMPX_GE_I32__GFX09                         0x000000d6
#define SQ_V_CMPX_GE_I64__GFX09                         0x000000f6
#define SQ_V_CMPX_GE_U16__GFX09                         0x000000be
#define SQ_V_CMPX_GE_U32__GFX09                         0x000000de
#define SQ_V_CMPX_GE_U64__GFX09                         0x000000fe
#define SQ_V_CMPX_GT_F16__GFX09                         0x00000034
#define SQ_V_CMPX_GT_F32__GFX09                         0x00000054
#define SQ_V_CMPX_GT_F64__GFX09                         0x00000074
#define SQ_V_CMPX_GT_I16__GFX09                         0x000000b4
#define SQ_V_CMPX_GT_I32__GFX09                         0x000000d4
#define SQ_V_CMPX_GT_I64__GFX09                         0x000000f4
#define SQ_V_CMPX_GT_U16__GFX09                         0x000000bc
#define SQ_V_CMPX_GT_U32__GFX09                         0x000000dc
#define SQ_V_CMPX_GT_U64__GFX09                         0x000000fc
#define SQ_V_CMPX_LE_F16__GFX09                         0x00000033
#define SQ_V_CMPX_LE_F32__GFX09                         0x00000053
#define SQ_V_CMPX_LE_F64__GFX09                         0x00000073
#define SQ_V_CMPX_LE_I16__GFX09                         0x000000b3
#define SQ_V_CMPX_LE_I32__GFX09                         0x000000d3
#define SQ_V_CMPX_LE_I64__GFX09                         0x000000f3
#define SQ_V_CMPX_LE_U16__GFX09                         0x000000bb
#define SQ_V_CMPX_LE_U32__GFX09                         0x000000db
#define SQ_V_CMPX_LE_U64__GFX09                         0x000000fb
#define SQ_V_CMPX_LG_F16__GFX09                         0x00000035
#define SQ_V_CMPX_LG_F32__GFX09                         0x00000055
#define SQ_V_CMPX_LG_F64__GFX09                         0x00000075
#define SQ_V_CMPX_LT_F16__GFX09                         0x00000031
#define SQ_V_CMPX_LT_F32__GFX09                         0x00000051
#define SQ_V_CMPX_LT_F64__GFX09                         0x00000071
#define SQ_V_CMPX_LT_I16__GFX09                         0x000000b1
#define SQ_V_CMPX_LT_I32__GFX09                         0x000000d1
#define SQ_V_CMPX_LT_I64__GFX09                         0x000000f1
#define SQ_V_CMPX_LT_U16__GFX09                         0x000000b9
#define SQ_V_CMPX_LT_U32__GFX09                         0x000000d9
#define SQ_V_CMPX_LT_U64__GFX09                         0x000000f9
#define SQ_V_CMPX_NEQ_F16__GFX09                        0x0000003d
#define SQ_V_CMPX_NEQ_F32__GFX09                        0x0000005d
#define SQ_V_CMPX_NEQ_F64__GFX09                        0x0000007d
#define SQ_V_CMPX_NE_I16__GFX09                         0x000000b5
#define SQ_V_CMPX_NE_I32__GFX09                         0x000000d5
#define SQ_V_CMPX_NE_I64__GFX09                         0x000000f5
#define SQ_V_CMPX_NE_U16__GFX09                         0x000000bd
#define SQ_V_CMPX_NE_U32__GFX09                         0x000000dd
#define SQ_V_CMPX_NE_U64__GFX09                         0x000000fd
#define SQ_V_CMPX_NGE_F16__GFX09                        0x00000039
#define SQ_V_CMPX_NGE_F32__GFX09                        0x00000059
#define SQ_V_CMPX_NGE_F64__GFX09                        0x00000079
#define SQ_V_CMPX_NGT_F16__GFX09                        0x0000003b
#define SQ_V_CMPX_NGT_F32__GFX09                        0x0000005b
#define SQ_V_CMPX_NGT_F64__GFX09                        0x0000007b
#define SQ_V_CMPX_NLE_F16__GFX09                        0x0000003c
#define SQ_V_CMPX_NLE_F32__GFX09                        0x0000005c
#define SQ_V_CMPX_NLE_F64__GFX09                        0x0000007c
#define SQ_V_CMPX_NLG_F16__GFX09                        0x0000003a
#define SQ_V_CMPX_NLG_F32__GFX09                        0x0000005a
#define SQ_V_CMPX_NLG_F64__GFX09                        0x0000007a
#define SQ_V_CMPX_NLT_F16__GFX09                        0x0000003e
#define SQ_V_CMPX_NLT_F32__GFX09                        0x0000005e
#define SQ_V_CMPX_NLT_F64__GFX09                        0x0000007e
#define SQ_V_CMPX_O_F16__GFX09                          0x00000037
#define SQ_V_CMPX_O_F32__GFX09                          0x00000057
#define SQ_V_CMPX_O_F64__GFX09                          0x00000077
#define SQ_V_CMPX_TRU_F16__GFX09                        0x0000003f
#define SQ_V_CMPX_TRU_F32__GFX09                        0x0000005f
#define SQ_V_CMPX_TRU_F64__GFX09                        0x0000007f
#define SQ_V_CMPX_T_I16__GFX09                          0x000000b7
#define SQ_V_CMPX_T_I32__GFX09                          0x000000d7
#define SQ_V_CMPX_T_I64__GFX09                          0x000000f7
#define SQ_V_CMPX_T_U16__GFX09                          0x000000bf
#define SQ_V_CMPX_T_U32__GFX09                          0x000000df
#define SQ_V_CMPX_T_U64__GFX09                          0x000000ff
#define SQ_V_CMPX_U_F16__GFX09                          0x00000038
#define SQ_V_CMPX_U_F32__GFX09                          0x00000058
#define SQ_V_CMPX_U_F64__GFX09                          0x00000078
#define SQ_V_CMP_CLASS_F16__GFX09                       0x00000014
#define SQ_V_CMP_CLASS_F32__GFX09                       0x00000010
#define SQ_V_CMP_CLASS_F64__GFX09                       0x00000012
#define SQ_V_CMP_EQ_F16__GFX09                          0x00000022
#define SQ_V_CMP_EQ_F32__GFX09                          0x00000042
#define SQ_V_CMP_EQ_F64__GFX09                          0x00000062
#define SQ_V_CMP_EQ_I16__GFX09                          0x000000a2
#define SQ_V_CMP_EQ_I32__GFX09                          0x000000c2
#define SQ_V_CMP_EQ_I64__GFX09                          0x000000e2
#define SQ_V_CMP_EQ_U16__GFX09                          0x000000aa
#define SQ_V_CMP_EQ_U32__GFX09                          0x000000ca
#define SQ_V_CMP_EQ_U64__GFX09                          0x000000ea
#define SQ_V_CMP_F_F16__GFX09                           0x00000020
#define SQ_V_CMP_F_F32__GFX09                           0x00000040
#define SQ_V_CMP_F_F64__GFX09                           0x00000060
#define SQ_V_CMP_F_I16__GFX09                           0x000000a0
#define SQ_V_CMP_F_I32__GFX09                           0x000000c0
#define SQ_V_CMP_F_I64__GFX09                           0x000000e0
#define SQ_V_CMP_F_U16__GFX09                           0x000000a8
#define SQ_V_CMP_F_U32__GFX09                           0x000000c8
#define SQ_V_CMP_F_U64__GFX09                           0x000000e8
#define SQ_V_CMP_GE_F16__GFX09                          0x00000026
#define SQ_V_CMP_GE_F32__GFX09                          0x00000046
#define SQ_V_CMP_GE_F64__GFX09                          0x00000066
#define SQ_V_CMP_GE_I16__GFX09                          0x000000a6
#define SQ_V_CMP_GE_I32__GFX09                          0x000000c6
#define SQ_V_CMP_GE_I64__GFX09                          0x000000e6
#define SQ_V_CMP_GE_U16__GFX09                          0x000000ae
#define SQ_V_CMP_GE_U32__GFX09                          0x000000ce
#define SQ_V_CMP_GE_U64__GFX09                          0x000000ee
#define SQ_V_CMP_GT_F16__GFX09                          0x00000024
#define SQ_V_CMP_GT_F32__GFX09                          0x00000044
#define SQ_V_CMP_GT_F64__GFX09                          0x00000064
#define SQ_V_CMP_GT_I16__GFX09                          0x000000a4
#define SQ_V_CMP_GT_I32__GFX09                          0x000000c4
#define SQ_V_CMP_GT_I64__GFX09                          0x000000e4
#define SQ_V_CMP_GT_U16__GFX09                          0x000000ac
#define SQ_V_CMP_GT_U32__GFX09                          0x000000cc
#define SQ_V_CMP_GT_U64__GFX09                          0x000000ec
#define SQ_V_CMP_LE_F16__GFX09                          0x00000023
#define SQ_V_CMP_LE_F32__GFX09                          0x00000043
#define SQ_V_CMP_LE_F64__GFX09                          0x00000063
#define SQ_V_CMP_LE_I16__GFX09                          0x000000a3
#define SQ_V_CMP_LE_I32__GFX09                          0x000000c3
#define SQ_V_CMP_LE_I64__GFX09                          0x000000e3
#define SQ_V_CMP_LE_U16__GFX09                          0x000000ab
#define SQ_V_CMP_LE_U32__GFX09                          0x000000cb
#define SQ_V_CMP_LE_U64__GFX09                          0x000000eb
#define SQ_V_CMP_LG_F16__GFX09                          0x00000025
#define SQ_V_CMP_LG_F32__GFX09                          0x00000045
#define SQ_V_CMP_LG_F64__GFX09                          0x00000065
#define SQ_V_CMP_LT_F16__GFX09                          0x00000021
#define SQ_V_CMP_LT_F32__GFX09                          0x00000041
#define SQ_V_CMP_LT_F64__GFX09                          0x00000061
#define SQ_V_CMP_LT_I16__GFX09                          0x000000a1
#define SQ_V_CMP_LT_I32__GFX09                          0x000000c1
#define SQ_V_CMP_LT_I64__GFX09                          0x000000e1
#define SQ_V_CMP_LT_U16__GFX09                          0x000000a9
#define SQ_V_CMP_LT_U32__GFX09                          0x000000c9
#define SQ_V_CMP_LT_U64__GFX09                          0x000000e9
#define SQ_V_CMP_NEQ_F16__GFX09                         0x0000002d
#define SQ_V_CMP_NEQ_F32__GFX09                         0x0000004d
#define SQ_V_CMP_NEQ_F64__GFX09                         0x0000006d
#define SQ_V_CMP_NE_I16__GFX09                          0x000000a5
#define SQ_V_CMP_NE_I32__GFX09                          0x000000c5
#define SQ_V_CMP_NE_I64__GFX09                          0x000000e5
#define SQ_V_CMP_NE_U16__GFX09                          0x000000ad
#define SQ_V_CMP_NE_U32__GFX09                          0x000000cd
#define SQ_V_CMP_NE_U64__GFX09                          0x000000ed
#define SQ_V_CMP_NGE_F16__GFX09                         0x00000029
#define SQ_V_CMP_NGE_F32__GFX09                         0x00000049
#define SQ_V_CMP_NGE_F64__GFX09                         0x00000069
#define SQ_V_CMP_NGT_F16__GFX09                         0x0000002b
#define SQ_V_CMP_NGT_F32__GFX09                         0x0000004b
#define SQ_V_CMP_NGT_F64__GFX09                         0x0000006b
#define SQ_V_CMP_NLE_F16__GFX09                         0x0000002c
#define SQ_V_CMP_NLE_F32__GFX09                         0x0000004c
#define SQ_V_CMP_NLE_F64__GFX09                         0x0000006c
#define SQ_V_CMP_NLG_F16__GFX09                         0x0000002a
#define SQ_V_CMP_NLG_F32__GFX09                         0x0000004a
#define SQ_V_CMP_NLG_F64__GFX09                         0x0000006a
#define SQ_V_CMP_NLT_F16__GFX09                         0x0000002e
#define SQ_V_CMP_NLT_F32__GFX09                         0x0000004e
#define SQ_V_CMP_NLT_F64__GFX09                         0x0000006e
#define SQ_V_CMP_O_F16__GFX09                           0x00000027
#define SQ_V_CMP_O_F32__GFX09                           0x00000047
#define SQ_V_CMP_O_F64__GFX09                           0x00000067
#define SQ_V_CMP_TRU_F16__GFX09                         0x0000002f
#define SQ_V_CMP_TRU_F32__GFX09                         0x0000004f
#define SQ_V_CMP_TRU_F64__GFX09                         0x0000006f
#define SQ_V_CMP_T_I16__GFX09                           0x000000a7
#define SQ_V_CMP_T_I32__GFX09                           0x000000c7
#define SQ_V_CMP_T_I64__GFX09                           0x000000e7
#define SQ_V_CMP_T_U16__GFX09                           0x000000af
#define SQ_V_CMP_T_U32__GFX09                           0x000000cf
#define SQ_V_CMP_T_U64__GFX09                           0x000000ef
#define SQ_V_CMP_U_F16__GFX09                           0x00000028
#define SQ_V_CMP_U_F32__GFX09                           0x00000048
#define SQ_V_CMP_U_F64__GFX09                           0x00000068
#define SQ_V_CNDMASK_B32__GFX09                         0x00000000
#define SQ_V_COS_F16__GFX09                             0x0000004a
#define SQ_V_COS_F32__GFX09                             0x0000002a
#define SQ_V_CUBEID_F32__GFX09                          0x000001c4
#define SQ_V_CUBEMA_F32__GFX09                          0x000001c7
#define SQ_V_CUBESC_F32__GFX09                          0x000001c5
#define SQ_V_CUBETC_F32__GFX09                          0x000001c6
#define SQ_V_CVT_F16_F32__GFX09                         0x0000000a
#define SQ_V_CVT_F16_I16__GFX09                         0x0000003a
#define SQ_V_CVT_F16_U16__GFX09                         0x00000039
#define SQ_V_CVT_F32_F16__GFX09                         0x0000000b
#define SQ_V_CVT_F32_F64__GFX09                         0x0000000f
#define SQ_V_CVT_F32_I32__GFX09                         0x00000005
#define SQ_V_CVT_F32_U32__GFX09                         0x00000006
#define SQ_V_CVT_F32_UBYTE0__GFX09                      0x00000011
#define SQ_V_CVT_F32_UBYTE1__GFX09                      0x00000012
#define SQ_V_CVT_F32_UBYTE2__GFX09                      0x00000013
#define SQ_V_CVT_F32_UBYTE3__GFX09                      0x00000014
#define SQ_V_CVT_F64_F32__GFX09                         0x00000010
#define SQ_V_CVT_F64_I32__GFX09                         0x00000004
#define SQ_V_CVT_F64_U32__GFX09                         0x00000016
#define SQ_V_CVT_FLR_I32_F32__GFX09                     0x0000000d
#define SQ_V_CVT_I16_F16__GFX09                         0x0000003c
#define SQ_V_CVT_I32_F32__GFX09                         0x00000008
#define SQ_V_CVT_I32_F64__GFX09                         0x00000003
#define SQ_V_CVT_NORM_I16_F16__GFX09                    0x0000004d
#define SQ_V_CVT_NORM_U16_F16__GFX09                    0x0000004e
#define SQ_V_CVT_OFF_F32_I4__GFX09                      0x0000000e
#define SQ_V_CVT_PKACCUM_U8_F32__GFX09                  0x000001f0
#define SQ_V_CVT_PKNORM_I16_F16__GFX09                  0x00000299
#define SQ_V_CVT_PKNORM_I16_F32__GFX09                  0x00000294
#define SQ_V_CVT_PKNORM_U16_F16__GFX09                  0x0000029a
#define SQ_V_CVT_PKNORM_U16_F32__GFX09                  0x00000295
#define SQ_V_CVT_PKRTZ_F16_F32__GFX09                   0x00000296
#define SQ_V_CVT_PK_I16_I32__GFX09                      0x00000298
#define SQ_V_CVT_PK_U16_U32__GFX09                      0x00000297
#define SQ_V_CVT_PK_U8_F32__GFX09                       0x000001dd
#define SQ_V_CVT_RPI_I32_F32__GFX09                     0x0000000c
#define SQ_V_CVT_U16_F16__GFX09                         0x0000003b
#define SQ_V_CVT_U32_F32__GFX09                         0x00000007
#define SQ_V_CVT_U32_F64__GFX09                         0x00000015
#define SQ_V_DIV_FIXUP_F16__GFX09                       0x00000207
#define SQ_V_DIV_FIXUP_F32__GFX09                       0x000001de
#define SQ_V_DIV_FIXUP_F64__GFX09                       0x000001df
#define SQ_V_DIV_FMAS_F32__GFX09                        0x000001e2
#define SQ_V_DIV_FMAS_F64__GFX09                        0x000001e3
#define SQ_V_DIV_SCALE_F32__GFX09                       0x000001e0
#define SQ_V_DIV_SCALE_F64__GFX09                       0x000001e1
#define SQ_V_EXP_F16__GFX09                             0x00000041
#define SQ_V_EXP_F32__GFX09                             0x00000020
#define SQ_V_EXP_LEGACY_F32__GFX09                      0x0000004b
#define SQ_V_FFBH_I32__GFX09                            0x0000002f
#define SQ_V_FFBH_U32__GFX09                            0x0000002d
#define SQ_V_FFBL_B32__GFX09                            0x0000002e
#define SQ_V_FLOOR_F16__GFX09                           0x00000044
#define SQ_V_FLOOR_F32__GFX09                           0x0000001f
#define SQ_V_FLOOR_F64__GFX09                           0x0000001a
#define SQ_V_FMA_F16__GFX09                             0x00000206
#define SQ_V_FMA_F32__GFX09                             0x000001cb
#define SQ_V_FMA_F64__GFX09                             0x000001cc
#define SQ_V_FRACT_F16__GFX09                           0x00000048
#define SQ_V_FRACT_F32__GFX09                           0x0000001b
#define SQ_V_FRACT_F64__GFX09                           0x00000032
#define SQ_V_FREXP_EXP_I16_F16__GFX09                   0x00000043
#define SQ_V_FREXP_EXP_I32_F32__GFX09                   0x00000033
#define SQ_V_FREXP_EXP_I32_F64__GFX09                   0x00000030
#define SQ_V_FREXP_MANT_F16__GFX09                      0x00000042
#define SQ_V_FREXP_MANT_F32__GFX09                      0x00000034
#define SQ_V_FREXP_MANT_F64__GFX09                      0x00000031
#define SQ_V_INTERP_MOV_F32__GFX09                      0x00000002
#define SQ_V_INTERP_P1LL_F16__GFX09                     0x00000274
#define SQ_V_INTERP_P1LV_F16__GFX09                     0x00000275
#define SQ_V_INTERP_P1_F32__GFX09                       0x00000000
#define SQ_V_INTERP_P2_F16__GFX09                       0x00000277
#define SQ_V_INTERP_P2_F32__GFX09                       0x00000001
#define SQ_V_INTRP_COUNT__GFX09                         0x00000004
#define SQ_V_INTRP_OFFSET__GFX09                        0x00000270
#define SQ_V_LDEXP_F16__GFX09                           0x00000033
#define SQ_V_LDEXP_F32__GFX09                           0x00000288
#define SQ_V_LDEXP_F64__GFX09                           0x00000284
#define SQ_V_LERP_U8__GFX09                             0x000001cd
#define SQ_V_LOG_F16__GFX09                             0x00000040
#define SQ_V_LOG_F32__GFX09                             0x00000021
#define SQ_V_LOG_LEGACY_F32__GFX09                      0x0000004c
#define SQ_V_LSHLREV_B16__GFX09                         0x0000002a
#define SQ_V_LSHLREV_B32__GFX09                         0x00000012
#define SQ_V_LSHLREV_B64__GFX09                         0x0000028f
#define SQ_V_LSHRREV_B16__GFX09                         0x0000002b
#define SQ_V_LSHRREV_B32__GFX09                         0x00000010
#define SQ_V_LSHRREV_B64__GFX09                         0x00000290
#define SQ_V_MAC_F16__GFX09                             0x00000023
#define SQ_V_MAC_F32__GFX09                             0x00000016
#define SQ_V_MAC_LEGACY_F32__GFX09                      0x0000028e
#define SQ_V_MADAK_F16__GFX09                           0x00000025
#define SQ_V_MADAK_F32__GFX09                           0x00000018
#define SQ_V_MADMK_F16__GFX09                           0x00000024
#define SQ_V_MADMK_F32__GFX09                           0x00000017
#define SQ_V_MAD_F16__GFX09                             0x00000203
#define SQ_V_MAD_F32__GFX09                             0x000001c1
#define SQ_V_MAD_I16__GFX09                             0x00000205
#define SQ_V_MAD_I32_I24__GFX09                         0x000001c2
#define SQ_V_MAD_I64_I32__GFX09                         0x000001e9
#define SQ_V_MAD_LEGACY_F32__GFX09                      0x000001c0
#define SQ_V_MAD_U16__GFX09                             0x00000204
#define SQ_V_MAD_U32_U24__GFX09                         0x000001c3
#define SQ_V_MAD_U64_U32__GFX09                         0x000001e8
#define SQ_V_MAX3_F32__GFX09                            0x000001d3
#define SQ_V_MAX3_I32__GFX09                            0x000001d4
#define SQ_V_MAX3_U32__GFX09                            0x000001d5
#define SQ_V_MAX_F16__GFX09                             0x0000002d
#define SQ_V_MAX_F32__GFX09                             0x0000000b
#define SQ_V_MAX_F64__GFX09                             0x00000283
#define SQ_V_MAX_I16__GFX09                             0x00000030
#define SQ_V_MAX_I32__GFX09                             0x0000000d
#define SQ_V_MAX_U16__GFX09                             0x0000002f
#define SQ_V_MAX_U32__GFX09                             0x0000000f
#define SQ_V_MBCNT_HI_U32_B32__GFX09                    0x0000028d
#define SQ_V_MBCNT_LO_U32_B32__GFX09                    0x0000028c
#define SQ_V_MED3_F32__GFX09                            0x000001d6
#define SQ_V_MED3_I32__GFX09                            0x000001d7
#define SQ_V_MED3_U32__GFX09                            0x000001d8
#define SQ_V_MIN3_F32__GFX09                            0x000001d0
#define SQ_V_MIN3_I32__GFX09                            0x000001d1
#define SQ_V_MIN3_U32__GFX09                            0x000001d2
#define SQ_V_MIN_F16__GFX09                             0x0000002e
#define SQ_V_MIN_F32__GFX09                             0x0000000a
#define SQ_V_MIN_F64__GFX09                             0x00000282
#define SQ_V_MIN_I16__GFX09                             0x00000032
#define SQ_V_MIN_I32__GFX09                             0x0000000c
#define SQ_V_MIN_U16__GFX09                             0x00000031
#define SQ_V_MIN_U32__GFX09                             0x0000000e
#define SQ_V_MOV_B32__GFX09                             0x00000001
#define SQ_V_MOV_FED_B32__GFX09                         0x00000009
#define SQ_V_MQSAD_PK_U16_U8__GFX09                     0x000001e6
#define SQ_V_MQSAD_U32_U8__GFX09                        0x000001e7
#define SQ_V_MSAD_U8__GFX09                             0x000001e4
#define SQ_V_MUL_F16__GFX09                             0x00000022
#define SQ_V_MUL_F32__GFX09                             0x00000005
#define SQ_V_MUL_F64__GFX09                             0x00000281
#define SQ_V_MUL_HI_I32__GFX09                          0x00000287
#define SQ_V_MUL_HI_I32_I24__GFX09                      0x00000007
#define SQ_V_MUL_HI_U32__GFX09                          0x00000286
#define SQ_V_MUL_HI_U32_U24__GFX09                      0x00000009
#define SQ_V_MUL_I32_I24__GFX09                         0x00000006
#define SQ_V_MUL_LEGACY_F32__GFX09                      0x00000004
#define SQ_V_MUL_LO_U16__GFX09                          0x00000029
#define SQ_V_MUL_LO_U32__GFX09                          0x00000285
#define SQ_V_MUL_U32_U24__GFX09                         0x00000008
#define SQ_V_NOP__GFX09                                 0x00000000
#define SQ_V_NOT_B32__GFX09                             0x0000002b
#define SQ_V_OP1_COUNT__GFX09                           0x00000080
#define SQ_V_OP1_OFFSET__GFX09                          0x00000140
#define SQ_V_OP2_COUNT__GFX09                           0x00000040
#define SQ_V_OP2_OFFSET__GFX09                          0x00000100
#define SQ_V_OP3_2IN_COUNT__GFX09                       0x00000080
#define SQ_V_OP3_2IN_OFFSET__GFX09                      0x00000280
#define SQ_V_OP3_3IN_COUNT__GFX09                       0x000000b0
#define SQ_V_OP3_3IN_OFFSET__GFX09                      0x000001c0
#define SQ_V_OP3_INTRP_COUNT__GFX09                     0x0000000c
#define SQ_V_OP3_INTRP_OFFSET__GFX09                    0x00000274
#define SQ_V_OPC_COUNT__GFX09                           0x00000100
#define SQ_V_OPC_OFFSET__GFX09                          0x00000000
#define SQ_V_OR_B32__GFX09                              0x00000014
#define SQ_V_PERM_B32__GFX09                            0x000001ed
#define SQ_V_QSAD_PK_U16_U8__GFX09                      0x000001e5
#define SQ_V_RCP_F16__GFX09                             0x0000003d
#define SQ_V_RCP_F32__GFX09                             0x00000022
#define SQ_V_RCP_F64__GFX09                             0x00000025
#define SQ_V_RCP_IFLAG_F32__GFX09                       0x00000023
#define SQ_V_READFIRSTLANE_B32__GFX09                   0x00000002
#define SQ_V_READLANE_B32__GFX09                        0x00000289
#define SQ_V_RNDNE_F16__GFX09                           0x00000047
#define SQ_V_RNDNE_F32__GFX09                           0x0000001e
#define SQ_V_RNDNE_F64__GFX09                           0x00000019
#define SQ_V_RSQ_F16__GFX09                             0x0000003f
#define SQ_V_RSQ_F32__GFX09                             0x00000024
#define SQ_V_RSQ_F64__GFX09                             0x00000026
#define SQ_V_SAD_HI_U8__GFX09                           0x000001da
#define SQ_V_SAD_U16__GFX09                             0x000001db
#define SQ_V_SAD_U32__GFX09                             0x000001dc
#define SQ_V_SAD_U8__GFX09                              0x000001d9
#define SQ_V_SIN_F16__GFX09                             0x00000049
#define SQ_V_SIN_F32__GFX09                             0x00000029
#define SQ_V_SQRT_F16__GFX09                            0x0000003e
#define SQ_V_SQRT_F32__GFX09                            0x00000027
#define SQ_V_SQRT_F64__GFX09                            0x00000028
#define SQ_V_SUBREV_F16__GFX09                          0x00000021
#define SQ_V_SUBREV_F32__GFX09                          0x00000003
#define SQ_V_SUBREV_U16__GFX09                          0x00000028
#define SQ_V_SUBREV_U32__GFX09                          0x00000036
#define SQ_V_SUB_F16__GFX09                             0x00000020
#define SQ_V_SUB_F32__GFX09                             0x00000002
#define SQ_V_SUB_I32__GFX09                             0x0000029d
#define SQ_V_SUB_U16__GFX09                             0x00000027
#define SQ_V_SUB_U32__GFX09                             0x00000035
#define SQ_V_TRIG_PREOP_F64__GFX09                      0x00000292
#define SQ_V_TRUNC_F16__GFX09                           0x00000046
#define SQ_V_TRUNC_F32__GFX09                           0x0000001c
#define SQ_V_TRUNC_F64__GFX09                           0x00000017
#define SQ_V_WRITELANE_B32__GFX09                       0x0000028a
#define SQ_V_XOR_B32__GFX09                             0x00000015
#define SQ_WAITCNT_EXP_SHIFT__GFX09                     0x00000004
#define SQ_WAITCNT_EXP_SIZE__GFX09                      0x00000003
#define SQ_WAITCNT_LGKM_SHIFT__GFX09                    0x00000008
#define SQ_WAITCNT_LGKM_SIZE__GFX09                     0x00000004
#define SQ_WAITCNT_VM_SHIFT__GFX09                      0x00000000
#define SQ_WAITCNT_VM_SIZE__GFX09                       0x00000004
#define SQ_WAVE_TYPE_PS0                                0x00000000
#define SQ_XLATE_VOP3_TO_VINTRP_COUNT__GFX09            0x00000004
#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET__GFX09           0x00000270
#define SQ_XLATE_VOP3_TO_VOP1_COUNT__GFX09              0x00000080
#define SQ_XLATE_VOP3_TO_VOP1_OFFSET__GFX09             0x00000140
#define SQ_XLATE_VOP3_TO_VOP2_COUNT__GFX09              0x00000040
#define SQ_XLATE_VOP3_TO_VOP2_OFFSET__GFX09             0x00000100
#define SQ_XLATE_VOP3_TO_VOPC_COUNT__GFX09              0x00000100
#define SQ_XLATE_VOP3_TO_VOPC_OFFSET__GFX09             0x00000000
#define SQ_XNACK_MASK_HI__GFX09                         0x00000069
#define SQ_XNACK_MASK_LO__GFX09                         0x00000068
#define UCONFIG_SPACE_END                               0x0000ffff
#define UCONFIG_SPACE_START                             0x0000c000
#define VMID_SZ                                         0x00000004
#define SQIND_WAVE_HWREGS_OFFSET__GFX09                 0x00000010
#define SQIND_WAVE_HWREGS_SIZE__GFX09                   0x000001f0
